Implements a full syntax parser for SystemVerilog.
- struct NodeMetadata
- Collection of metadata that can be associated with a syntax node at parse time.
- auto parseCompilationUnit() -> CompilationUnitSyntax&
- Parse a whole compilation unit.
- auto parseExpression() -> ExpressionSyntax&
- auto parseGuess() -> SyntaxNode&
- auto isDone() -> bool
- Check whether the parser has consumed the entire input stream.
- auto getEOFToken() -> Token
- Gets the EndOfFile token, if one has been consumed. Otherwise returns an empty token.
- auto getMetadataMap() -> MetadataMap&&
- auto getGlobalInstantiations() -> NameSet&&
Parse an expression / statement / module / class / name. These are mostly for testing; only use if you know that the source stream is currently looking at one of these.
Generalized node parse function that tries to figure out what we're looking at and parse that specifically. A normal batch compile won't call this, since in a well formed program every file is a compilation unit, but for snippets of code this can be convenient.
Gets metadata that was in effect when certain syntax nodes were parsed (such as various bits of preprocessor state).
Gets a set of names of all instantiations of global modules/interfaces/programs. This can be used to determine which modules should be considered as top-level roots of the design.