Language Support

Overview of supported language features.

This is an overview of which SystemVerilog features slang supports, and those which it yet does not. This is not a promise that features marked "supported" are bug-free, but should imply that any such bugs are as of yet unknown and should be reported if discovered.

Features are expressed via references to chapters and sections within the IEEE 1800-2017 SystemVerilog Language Reference Manual (LRM).

Elaboration

Chapters 1-4

LRMFeatureSupported
1OverviewN/A
2Normative referencesN/A
3Design and verification building blocksN/A
4Scheduling semanticsN/A

5. Lexical conventions

LRMFeatureSupported
5.2Lexical tokensv0.2
5.3White spacev0.2
5.4Commentsv0.2
5.5Operatorsv0.2
5.6Identifiers and keywordsv0.2
5.7Numbersv0.2
5.8Time literalsv0.3
5.9String literalsv0.2
5.10Structure literalsv0.2
5.11Array literalsv0.2
5.12Attributesv0.2
5.13Built-in methodsv0.2

6. Data types

LRMFeatureSupported
6.2Data typesv0.2
6.3Value setv0.2
6.4Singular and aggregate typesv0.2
6.5Nets and variablesv0.2
6.6Net typesv0.2
6.6.7User-defined nettypesv1.0
6.6.8Generic interconnectv1.0
6.7Net declarationsv0.6
6.8Variable declarationsv0.2
6.9Vector declarationsv0.2
6.10Implicit declarationsv0.3
6.11Integer typesv0.2
6.12Real typesv0.2
6.13Void typev0.2
6.14Chandle typesv0.5
6.15Classesv0.5
6.16Stringsv0.2
6.17Eventsv0.5
6.18User-defined typesv0.2
6.19Enumerationsv0.2
6.20.2Value parametersv0.2
6.20.2.1$ as a parameter valuev0.8
6.20.3Type parametersv0.2
6.20.4Local parametersv0.2
6.20.5Specify parametersv0.7
6.20.6Const constantsv0.3
6.21Scope and lifetimev0.3
6.22Type compatibilityv0.2
6.23Type operatorv0.7
6.24.1Static castingv0.2
6.24.2Dynamic castingv0.5
6.24.3Bit-stream castingv0.5
6.25Parameterized data typesv0.5

7. Aggregate data types

LRMFeatureSupported
7.2Structuresv0.2
7.3Unionsv0.9
7.4Packed and unpacked arraysv0.2
7.5Dynamic arraysv0.4
7.6Array assignmentsv0.2
7.7Arrays as arguments to subroutinesv0.2
7.8Associative arraysv0.4
7.9Associative array methodsv0.6
7.10Queuesv0.7
7.11Array querying functionsv0.6
7.12Array manipulation methodsv0.6

8. Classes

LRMFeatureSupported
8.3Syntaxv0.2
8.4Objectsv0.5
8.5Object propertiesv0.5
8.6Object methodsv0.5
8.7Constructorsv0.5
8.8Typed constructor callsv0.5
8.9Static class propertiesv0.5
8.10Static methodsv0.5
8.11Thisv0.5
8.12Assignment, renaming, and copyingv0.5
8.13Inheritance and subclassesv0.5
8.14Overriden membersv0.5
8.15Superv0.5
8.16Castingv0.5
8.17Chaining constructorsv0.5
8.18Data hiding and encapsulationv0.5
8.19Constant class propertiesv0.5
8.20Virtual methodsv0.5
8.21Abstract classes and pure virtual methodsv0.5
8.22Polymorphism: dynamic method lookupv0.5
8.23Class scope resolution operatorv0.5
8.24Out-of-block declarationsv0.5
8.25Parameterized classesv0.5
8.26Interface classesv0.5
8.27Typedef classv0.5
8.28Classes and structuresN/A
8.29Memory managementN/A

9. Processes

LRMFeatureSupported
9.2.1Initial proceduresv0.2
9.2.2Always proceduresv0.2
9.2.3Final proceduresv0.2
9.3.1Sequential blocksv0.2
9.3.2Parallel blocksv0.2
9.3.3Statement block start and finish timesv0.2
9.3.4Block namesv0.2
9.3.5Statement labelsv0.2
9.4.1Delay controlv0.2
9.4.2Event controlv0.2
9.4.2.3Conditional event controlsv0.6
9.4.2.4Sequence eventsv0.8
9.4.3Level-sensitive event controlv0.6
9.4.4Level-sensitive sequence controlsv0.8
9.4.5Intra-assignment timing controlsv0.6
9.5Process execution threadsN/A
9.6.1Wait fork statementv0.4
9.6.2Disable statementv0.4
9.6.3Disable fork statementv0.4
9.7Fine-grain process controlv0.6

10. Assignment statements

LRMFeatureSupported
10.3Continuous assignmentsv0.7
10.4Procedural assignmentsv0.2
10.5Variable declarations assignmentv0.2
10.6Procedural continuous assignmentsv0.7
10.7Assignment extension and truncationv0.2
10.8Assignment-like contextsv0.2
10.9Assignment patternsv5.0
10.10Unpacked array concatenationv0.4
10.11Net aliasingv4.0

11. Operators and expressions

LRMFeatureSupported
11.3Operatorsv0.2
11.4Operator descriptionsv0.2
11.4.14Streaming operatorsv0.5
11.5Operandsv0.2
11.6Expression bit lengthsv0.2
11.7Signed expressionsv0.2
11.8Expression evaluation rulesv0.2
11.9Tagged union expressionsv0.9
11.10String literal expressionsv0.5
11.11Min/typ/max expressionsv0.4
11.12Let constructv0.9

12. Procedural programming statements

LRMFeatureSupported
12.4Conditional if-else statementv0.2
12.5Case statementv0.2
12.6Pattern matching conditional statementsv2.0
12.7.1For-loop statementsv0.2
12.7.2Repeat-loop statementsv0.2
12.7.3Foreach-loop statementsv0.2
12.7.4While-loop statementsv0.2
12.7.5Do...while-loop statementsv0.2
12.7.6Forever-loop statementsv0.2
12.8Jump statementsv0.2

13. Tasks and functions

LRMFeatureSupported
13.3Tasksv0.2
13.3.2Task memory usage and concurrent activationv0.7
13.4Functionsv0.2
13.4.4Background processes spawned by function callsv0.7
13.5Subroutine calls and argument passingv0.7
13.6Import and export functionsv0.6
13.7Task and function namesv0.2
13.8Parameterized tasks and functionsN/A

14. Clocking blocks

LRMFeatureSupported
14.3Clocking block declarationv0.8
14.4Input and output skewsv0.8
14.5Hierarchical expressionsv0.8
14.6Signals in multiple clocking blocksv0.8
14.7Clocking block scope and lifetimev0.8
14.8Multiple clocking blocks examplev0.8
14.9Interfaces and clocking blocksv0.8
14.10Clocking block eventsv0.8
14.11Cycle delayv0.8
14.12Default clockingv0.8
14.13Input samplingN/A
14.14Global clockingv0.8
14.15Synchronous eventsv0.8
14.16Synchronous drivesv0.8

15. Interprocess synchronization and communication

LRMFeatureSupported
15.3Semaphoresv0.6
15.4Mailboxesv1.0
15.5Named eventsv0.5

16. Assertions

LRMFeatureSupported
16.3Immediate assertionsv0.2
16.4Deferred assertionsv0.8
16.5Concurrent assertions overviewv0.8
16.6Boolean expressionsv0.8
16.7Sequencesv0.8
16.8Declaring sequencesv0.8
16.9Sequence operationsv0.8
16.10Local variablesv0.8
16.11Calling subroutines on match of sequencev0.8
16.12Declaring propertiesv0.8
16.12.22Nondegeneracypartial
16.13Multiclock supportpartial
16.14Concurrent assertionsv0.8
16.14.7Inferred value functionspartial
16.15Disable iff resolutionv0.8
16.16Clock resolutionno
16.17Expect statementv0.8
16.18Clocking blocks and concurrent assertionsN/A

17. Checkers

LRMFeatureSupported
17.2Checker declarationv4.0
17.3Checker instantiationv4.0
17.4Context inferencev4.0
17.5Checker proceduresv4.0
17.6Covergroups in checkersv4.0
17.7Checker variablesv4.0
17.8Functions in checkersv4.0
17.9Complex checker examplev4.0

18. Constrained random value generation

LRMFeatureSupported
18.3Concepts and usagev0.6
18.4Random variablesv0.6
18.5Constraint blocksv0.6
18.6Randomization methodsv0.6
18.7In-line constraintsv0.6
18.8Disabling random variablesv0.6
18.9Controlling constraintsv0.6
18.10Dynamic constraint modificationN/A
18.11In-line random variable controlv0.6
18.12Randomization of scope variablesv0.6
18.13Random number system functionsv0.6
18.14Random stabilityN/A
18.15Manually seeding randomizeN/A
18.16Random weighted casev0.9
18.17Random sequence generationv0.9

19. Functional coverage

LRMFeatureSupported
19.3Defining the coverage modelv1.0
19.4Using covergroup in classesv1.0
19.5Defining coverage pointsv1.0
19.6Defining cross coveragev1.0
19.7Specifying coverage optionsv1.0
19.8Predefined coverage methodsv1.0
19.9Predefined coverage system tasksv0.9
19.10Organization of option membersv1.0
19.11Coverage computationN/A

20. Utility system tasks and system functions

LRMFeatureSupported
20.2Simulation control tasksv0.2
20.3Simulation time functionsv0.2
20.4Timescale tasksv0.4
20.5Conversion functionsv0.2
20.6Data query functionsv0.3
20.6.1Range system functionv0.8
20.7Array query functionsv0.4
20.8Math functionsv0.2
20.9Bit vector system functionsv0.2
20.10Severity tasksv0.2
20.11Elaboration tasksv0.5
20.12Assertion control tasksv0.6
20.13Sampled value system functionsv0.8
20.14Coverage control functionsv0.9
20.15Probabilistic distribution functionsv0.7
20.16Stochastic analysis tasks and functionsv0.7
20.17PLA modeling tasksv0.9
20.18Miscellaneous tasks and functionsv0.4

21. Input/output system tasks and system functions

LRMFeatureSupported
21.2Display system tasksv0.2
21.3File I/O tasks and functionsv0.4
21.4Loading memory array data from filev0.2
21.5Writing memory array data to filev0.2
21.6Command line inputv0.2
21.7Value change dump filesv0.4

22. Compiler directives

LRMFeatureSupported
22.3`resetallv0.2
22.4`includev0.2
22.5`define, `undef, and `undefineallv0.2
22.6`ifdef, `else, `elsif, `endif, `ifndefv0.2
22.7`timescalev0.2
22.8`default_nettypev0.2
22.9`unconnected_drive and `nounconnected_drivev0.3
22.10`celldefine and `endcelldefinev0.2
22.11`pragmav0.3
22.12`linev0.2
22.13`__FILE__ and `__LINE__v0.2
22.14`begin_keywords, `end_keywordsv0.2

23. Modules and hierarchy

LRMFeatureSupported
23.2.1Module definitionsv0.2
23.2.2Port declarationsv1.0
23.2.3Parameterized modulesv0.2
23.2.4Module contentsv0.2
23.3.1Top-level modules and $rootv0.2
23.3.2Module instantiation syntaxv0.2
23.3.3Port connection rulesv1.0
23.4Nested modulesv1.0
23.5Extern modulesv4.0
23.6Hierarchical namesv0.2
23.7Member selects and hierarchical namesv0.2
23.8Upwards name referencingv0.7
23.9Scope rulesv0.2
23.10Overriding module parametersv0.2
23.10.1defparam statementv3.0
23.11Binding auxiliary code to scopes or instancesv3.0

24. Programs

LRMFeatureSupported
24.3The program constructv3.0
24.4Eliminating testbench racesN/A
24.5Blocking tasks in cycle/event modev3.0
24.6Programwide space and anonymous programsv3.0
24.7Program control tasksv0.2

25. Interfaces

LRMFeatureSupported
25.3Interface syntaxv0.2
25.4Ports in interfacesv0.2
25.5Modportsv0.6
25.5.4Modport expressionsv2.0
25.5.5Clocking blocks and modportsv2.0
25.6Interfaces and specify blocksv3.0
25.7Tasks and functions in interfacesv2.0
25.8Parameterized interfacesv0.2
25.9Virtual interfacespartial
25.10Access to interface objectsv0.6

26. Packages

LRMFeatureSupported
26.2Package declarationsv0.2
26.3Referencing data in packagesv0.2
26.4Using packages in module headersv0.2
26.5Search order rulesv0.2
26.6Exporting imported names from packagesv0.9
26.7The std built-in packagev0.6

27. Generate constructs

LRMFeatureSupported
27.3Generate construct syntaxv0.2
27.4Loop generate constructsv0.2
27.5Conditional generate constructsv0.2
27.6External names for unnamed generate blocksv0.4

28. Gate-level and switch-level modeling

LRMFeatureSupported
28.3Gate and switch declaration syntaxv0.7
28.4and, nand, nor, or, xor, and xnor gatesv0.7
28.5buf and not gatesv0.7
28.6bufif1, bufif0, notif1, and notif0 gatesv0.7
28.7MOS switchesv0.7
28.8Bidirectional pass switchesv0.7
28.9CMOS switchesv0.7
28.10pullup and pulldown sourcesv0.7
28.11Logic strength modelingN/A
28.12Strengths and values of combined signalsN/A
28.13Strength reduction by nonresistive devicesN/A
28.14Strength reduction by resistive devicesN/A
28.15Strengths of net typesN/A
28.16Gate and net delaysv0.7

29. User-defined primitives

LRMFeatureSupported
29.3UDP definitionv4.0
29.4Combinational UDPsv4.0
29.5Level-sensitive sequential UDPsv4.0
29.6Edge-sensitive sequential UDPsv4.0
29.7Sequential UDP initializationv0.7
29.8UDP instancesv0.7
29.9Mixing level-sensitive and edge-sensitive descriptionsN/A
29.10Level-sensitive dominanceN/A

30. Specify blocks

LRMFeatureSupported
30.3Specify block declarationv3.0
30.4Module path declarationsv3.0
30.5Assigning delays to module pathsv3.0
30.6Mixing module path delays and distributed delaysN/A
30.7Detailed control of pulse filtering behaviorv3.0

31. Timing checks

LRMFeatureSupported
31.2Overviewv3.0
31.3Timing checks using a stability windowv3.0
31.4Timing checks for clock and control signalsv3.0
31.5Edge-control specifiersv3.0
31.6Notifiers: user-defined responses to timing violationsv3.0
31.7Enabling timing checks with conditioned eventsv3.0
31.8Vector signals in timing checksv3.0
31.9Negative timing checksv3.0

32. Backannotation using the standard delay format

LRMFeatureSupported
32.3The SDF annotatorN/A
32.4Mapping of SDF constructs to SystemVerilogN/A
32.5Multiple annotationsN/A
32.6Multiple SDF filesN/A
32.7Pulse limit annotationN/A
32.8SDF to SystemVerilog delay value mappingN/A
32.9Loading timing data from an SDF filev0.7

33. Configuring the contents of a design

LRMFeatureSupported
33.2Overviewpartial
33.3Librariesv4.0
33.4Configurationspartial
33.5Using libraries and configsv5.0
33.6Configuration examplespartial
33.7Displaying library binding informationpartial
33.8Library mapping examplesv4.0

34. Protected envelopes

LRMFeatureSupported
34.2OverviewN/A
34.3Processing protected envelopesN/A
34.4Protect pragma directivesv2.0
34.5Protect pragma keywordsv2.0

35. Direct programming interface

LRMFeatureSupported
35.2Overviewv0.6
35.3Two layers of DPIN/A
35.4Global namespace of imported and exported functionsv0.6
35.5Imported tasks and functionsv0.6
35.5.6.1Open arraysv3.0
35.6Calling imported functionsv0.6
35.7Exported functionsv0.6
35.8Exported tasksv0.6
35.9Disabling DPI tasks and functionsN/A

Simulation

Simulation is not yet supported at all, but it will be at some point in the future.