Warning Reference

-Warith-in-shift

Identifies an arithmetic operator used in a shift expression, which can indicate a mistake in the intended order of operations.

Example:

module m;
    logic a;
    initial begin
        if (a << 1 + 1) begin end
    end
endmodule

produces:

test.sv:4:20: warning: '<<' has lower precedence than '+'; '+' will be evaluated first [-Warith-in-shift]
        if (a << 1 + 1) begin end
              ~~ ~~^~~
test.sv:4:20: note: place parentheses around the '+' expression to silence this warning
        if (a << 1 + 1) begin end
                 ~~^~~

-Warith-op-mismatch

An arithmetic operator has operands of different types – one or both will be converted before the operation is performed. This is not necessarily a problem but the warning can be helpful if you prefer to be strict about disallowing implicit conversions.

Example:

module m;
    logic [7:0] a;
    struct packed { logic [7:0] x; } b;
    initial a += b;
endmodule

produces:

test.sv:4:15: warning: arithmetic between operands of different types ('logic[7:0]' and '<unnamed packed struct>') [-Warith-op-mismatch]
    initial a += b;
            ~ ^~ ~

-Wbad-procedural-force

According to the Verilog/SystemVerilog standard, it is illegal to procedurally force a bit-select or range select of a variable (you can do that with a net, or with a plain variable). It is an error by default, but can be turned into a warning, to support code compatibility with commercial tools that accept this illegal code.

This diagnostic is enabled by default.

Example:

module m;
    reg [1:0]r;
    initial
        force r[0] = 1'b0;
endmodule

produces:

test.sv:4:15: warning: lvalue of force/release must be a net, a variable, a constant select of a net, or a concatenation of these [-Wbad-procedural-force]
        force r[0] = 1'b0;
              ^~~~

-Wbitwise-op-mismatch

A bitwise operator has operands of different types – one or both will be converted before the operation is performed. This is not necessarily a problem but the warning can be helpful if you prefer to be strict about disallowing implicit conversions.

Example:

module m;
    logic [7:0] a;
    logic [11:1] b;
    initial a = a | b;
endmodule

produces:

test.sv:4:19: warning: bitwise operation between operands of different types ('logic[7:0]' and 'logic[11:1]') [-Wbitwise-op-mismatch]
    initial a = a | b;
                ~ ^ ~

-Wbitwise-op-parentheses

Identifies a mix of bitwise operators with different levels of precedence without any parentheses, which can indicate a mistake in the intended order of operations.

Example:

module m;
    logic a, b, c;
    initial begin
        if (a & b | c) begin end
    end
endmodule

produces:

test.sv:4:15: warning: '&' within '|' [-Wbitwise-op-parentheses]
        if (a & b | c) begin end
            ~~^~~ ~
test.sv:4:15: note: place parentheses around the '&' expression to silence this warning
        if (a & b | c) begin end
            ~~^~~

-Wbitwise-rel-precedence

Identifies a bitwise operator used in a relational expression without parentheses, which can indicate a mistake in the intended order of operations.

Example:

module m;
    int unsigned flags;
    initial begin
        if (flags & 'h1 == 'h1) begin end
    end
endmodule

produces:

test.sv:4:19: warning: '&' has lower precedence than '=='; '==' will be evaluated first [-Wbitwise-rel-precedence]
        if (flags & 'h1 == 'h1) begin end
                  ^ ~~~~~~~~~~
test.sv:4:13: note: place parentheses around the '&' expression to evaluate it first
        if (flags & 'h1 == 'h1) begin end
            ^~~~~~~~~~~
test.sv:4:21: note: place parentheses around the '==' expression to silence this warning
        if (flags & 'h1 == 'h1) begin end
                    ^~~~~~~~~~

-Wcase-default

A case statement is missing a 'default' label. This is not necessarily problematic, but some coding standards mandate that all case statements include a 'default' so this warning can be used to enforce that.

Example:

module m;
    enum {A, B} e;
    initial begin
        case (e)
            A, B: ;
        endcase
    end
endmodule

produces:

test.sv:4:9: warning: 'case' missing 'default' label [-Wcase-default]
        case (e)
        ^~~~

-Wcase-dup

A case statement contains more than one item with the same value. Case items are evaluated and selected in order and so the second one will never be matched.

Example:

module m;
    int i;
    initial begin
        case (i)
            1, 2:;
            3, 1:;
            default;
        endcase
    end
endmodule

produces:

test.sv:6:16: warning: 'case' statement contains duplicate items for value '1' (the second one will never be matched) [-Wcase-dup]
            3, 1:;
               ^
test.sv:5:13: note: previous usage here
            1, 2:;
            ^

-Wcase-enum

A case statement with an enum type condition does not include items that cover every enumerand. Note that this warning will not be issued if there is a 'default' label.

Example:

module m;
    enum {A, B} e;
    initial begin
        case (e)
            A: ;
        endcase
    end
endmodule

produces:

test.sv:4:15: warning: enumeration value 'B' not handled in case statement [-Wcase-enum]
        case (e)
              ^

-Wcase-enum-explicit

A case statement with an enum type condition does not include items that cover every enumerand, regardless of whether there is a default label or not.

Example:

module m;
    enum {A, B} e;
    initial begin
        case (e)
            A: ;
            default;
        endcase
    end
endmodule

produces:

test.sv:4:15: warning: enumeration value 'B' not explicitly handled in case statement [-Wcase-enum-explicit]
        case (e)
              ^

-Wcase-gen-dup

More than one case generate item was found to have the same value. The second case block will never be selected.

Example:

module m;
    case (1)
        1: begin end
        1: begin end
    endcase
endmodule

produces:

test.sv:4:9: warning: more than one case generate block matches the value 1 [-Wcase-gen-dup]
        1: begin end
        ^
test.sv:3:9: note: previous match here
        1: begin end
        ^

-Wcase-gen-none

A case generate directive did not match any items and so no block was selected.

Example:

module m;
    case (1)
        0: begin end
    endcase
endmodule

produces:

test.sv:2:11: warning: no case generate expression matches the value 1 [-Wcase-gen-none]
    case (1)
          ^

-Wcase-not-wildcard

A normal case statement has items with integer literals that contain X or Z bits. These bits don't count as wildcards, so the designer may have meant for this to be a 'casex' or 'casez' statement instead.

Example:

module m;
    logic [2:0] a;
    initial begin
        case (a)
            3'b10?:;
        endcase
    end
endmodule

produces:

test.sv:5:13: warning: 'case' statement item has unknown bits which don't work as wildcards; should this be a 'casex' or 'casez' statement? [-Wcase-not-wildcard]
            3'b10?:;
            ^~~~~~

-Wcase-outside-range

A case item has a known value that makes it impossible to ever match the case condition (or vice versa).

Example:

module m;
    logic [2:0] a;
    initial begin
        case (a)
            4'b1000: ;
        endcase
    end
endmodule

produces:

test.sv:5:13: warning: 'case' item with 4 bits can never match the 3 bit case expression [-Wcase-outside-range]
            4'b1000: ;
            ^~~~~~~

-Wcase-overlap

A wildcard case statement contains overlapping items, which can be confusing since the overlapping value(s) will only ever match the first item in the list.

Example:

module m;
    logic [3:0] a;
    initial begin
        casez (a)
            4'b1011:;
            4'b101?:;
            default;
        endcase
    end
endmodule

produces:

test.sv:6:13: warning: 'casez' statement contains overlapping items [-Wcase-overlap]
            4'b101?:;
            ^~~~~~~
test.sv:5:13: note: previous usage here
            4'b1011:;
            ^~~~~~~

-Wcase-type

The type of a case item expression does not match the type of the case condition expression.

Example:

module m;
    enum {A, B} e;
    enum {C, D} f;
    initial begin
        case (e)
            C: ;
        endcase
    end
endmodule

produces:

test.sv:6:13: warning: comparison of different types in 'case' statement ('<unnamed enum>' and '<unnamed enum>') [-Wcase-type]
            C: ;
            ^

-Wcasez-with-x

A 'casez' statement has items with integer literals that contain X bits. These bits don't count as wildcards, so the designer may have meant for this to be a 'casex' statement instead.

Example:

module m;
    logic [2:0] a;
    initial begin
        casez (a)
            3'b10x:;
        endcase
    end
endmodule

produces:

test.sv:5:13: warning: 'casez' statement item has 'x' bits which don't work as wildcards; should this be a 'casex' statement? [-Wcasez-with-x]
            3'b10x:;
            ^~~~~~

-Wcomparison-mismatch

A comparison operator has operands of different types – one or both will be converted before the operation is performed. This is not necessarily a problem but the warning can be helpful if you prefer to be strict about disallowing implicit conversions.

Example:

module m;
    logic [7:0] a;
    struct packed { logic [7:0] x; } b;
    initial begin
        if (a == b) begin
        end
    end
endmodule

produces:

test.sv:5:15: warning: comparison between operands of different types ('logic[7:0]' and '<unnamed packed struct>') [-Wcomparison-mismatch]
        if (a == b) begin
            ~ ^~ ~

-Wconditional-precedence

Identifies a conditional expression mixed with a binary expression in way that suggests a different intended order of operations.

Example:

module m;
    logic a, b;
    initial begin
        if ((a + b ? 1 : 2) == 2) begin end
    end
endmodule

produces:

test.sv:4:20: warning: operator '?:' has lower precedence than '+'; '+' will be evaluated first [-Wconditional-precedence]
        if ((a + b ? 1 : 2) == 2) begin end
             ~~~~~ ^
test.sv:4:18: note: place parentheses around the '?:' expression to evaluate it first
        if ((a + b ? 1 : 2) == 2) begin end
                 ^~~~~~~~~
test.sv:4:14: note: place parentheses around the '+' expression to silence this warning
        if ((a + b ? 1 : 2) == 2) begin end
             ^~~~~

-Wconsecutive-comparison

Identifies a sequence of comparison operators that suggest an incorrect notion of how the comparisons will be evaluated.

Example:

module m;
    logic a, b, c;
    initial begin
        if (a < b < c) begin end
    end
endmodule

produces:

test.sv:4:19: warning: comparisons like 'x < y < z' don't have their mathematical meaning [-Wconsecutive-comparison]
        if (a < b < c) begin end
                  ^

-Wconstant-conversion

A constant value is changed (truncated) by an implicit conversion.

Example:

module m;
    logic [9:0] a = 9000;
endmodule

produces:

test.sv:2:19: warning: implicit conversion from 'logic signed[31:0]' to 'logic[9:0]' changes value from 9000 to 10'd808 [-Wconstant-conversion]
    logic [9:0] a = 9000;
                  ^ ~~~~

-Wconstraint-missing

An implicit class constraint block has no external definition and so is useless.

This diagnostic is enabled by default.

Example:

class C;
    constraint c;
endclass

produces:

test.sv:2:16: warning: no body for implicit constraint block 'c' [-Wconstraint-missing]
    constraint c;
               ^

-Wconversion

Controls -Wwidth-trunc, -Wwidth-expand, -Wport-width-trunc, -Wport-width-expand, -Wimplicit-conv, -Wconstant-conversion, -Wsign-conversion, -Wfloat-bool-conv, -Wint-bool-conv, -Wfloat-int-conv, -Wint-float-conv, -Wfloat-widen, -Wfloat-narrow, -Wpacked-array-conv, -Wcase-type.

-Wdpi-pure-task

A DPI import task is marked 'pure', which is disallowed by SystemVerilog but can be downgraded to a warning to support code compatibility with other tools.

This diagnostic is enabled by default.

Example:

import "DPI-C" pure task func(logic [3:0] a);

produces:

test.sv:1:21: warning: DPI tasks cannot be marked 'pure' [-Wdpi-pure-task]
import "DPI-C" pure task func(logic [3:0] a);
               ~~~~ ^~~~

-Wdpi-spec

Old-style "DPI" specified subroutines are deprecated and not supported by slang. Use the new-style "DPI-C" which has a well-defined standardized calling convention.

This diagnostic is enabled by default.

Example:

import "DPI" function void foo();

produces:

test.sv:1:8: warning: 'DPI' specified subroutines are not supported and will be treated as 'DPI-C'. Note that this may require changes to the application's C code. [-Wdpi-spec]
import "DPI" function void foo();
       ^~~~~

-Wdup-attr

A design element has more than one attribute of the same name. Only the last one will apply.

Example:

module m;
    (* foo = 1, foo = 2 *)
    int i;
endmodule

produces:

test.sv:2:17: warning: duplicate attribute definition 'foo'; taking last value [-Wdup-attr]
    (* foo = 1, foo = 2 *)
                ^

-Wdup-config-rule

More than one rule in a configuration targets the same cell or instance. They can't both be used, so slang takes the first one and ignores all others.

This diagnostic is enabled by default.

Example:

module d;
endmodule

config cfg;
    design d;
    instance d.foo use bar;
    instance d.foo use baz;
endconfig

produces:

test.sv:7:5: warning: duplicate config rule for instance 'd.foo' -- ignoring this one [-Wdup-config-rule]
    instance d.foo use baz;
    ^~~~~~~~~~~~~~~~~~~~~~~
test.sv:6:5: note: previous definition here
    instance d.foo use bar;
    ^~~~~~~~~~~~~~~~~~~~~~~

-Wdup-import

A given scope contains more than one import statement for the same package and name.

Example:

package p;
    int i;
endpackage

module m;
    import p::i;
    import p::i;
endmodule

produces:

test.sv:7:15: warning: duplicate import declaration is redundant [-Wdup-import]
    import p::i;
              ^
test.sv:6:15: note: previous definition here
    import p::i;
              ^

-Wdup-timing-path

More than one specify timing path was given for a particular pair of input and output terminals in a module.

This diagnostic is enabled by default.

Example:

module m(input a, output b);
    specify
        (a => b) = 1;
        (a => b) = 2;
    endspecify
endmodule

produces:

test.sv:4:10: warning: duplicate timing path [-Wdup-timing-path]
        (a => b) = 2;
         ^    ~
test.sv:3:10: note: previous definition here
        (a => b) = 1;
         ^    ~

-Wduplicate-definition

A module has been defined using the same name as a previously defined module. This is an error by default but can be downgraded to a warning for compatibility with other tools. This applies to both top level modules as well as nested modules (but only duplicated nested modules within the same scope, as it is OK to have modules with the same name in different scopes).

This diagnostic is enabled by default.

Example:

module a;
endmodule;

module a;
endmodule

produces:

test.sv:1:8: error: redefinition of 'a'
module a;
       ^
test.sv:4:8: note: previous definition here
module a;
       ^
test.sv:4:8: warning: duplicate definition of 'a' [-Wduplicate-definition]
module a;
       ^
test.sv:1:8: note: previous definition here
module a;
       ^

-Wduplicate-defparam

More than one defparam targets the same parameter. The LRM specifies that this is undefined behavior. slang takes the value from the first defparam it sees and ignores the rest.

This diagnostic is enabled by default.

Example:

module m;
    parameter p = 1;
endmodule

module n;
    defparam m1.p = 3;
endmodule

module top;
    m m1();
    n n1();
    defparam m1.p = 2;
endmodule

produces:

test.sv:12:14: warning: parameter already has a defparam override applied; ignoring this one [-Wduplicate-defparam]
    defparam m1.p = 2;
             ^~~~~~~~
test.sv:6:14: note: previous definition here
    defparam m1.p = 3;
             ^~~~~~~~

-Wdynarray-index

A constant function tried to access a nonexistent element of a dynamic array.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    automatic int i[] = new [2];
    return i[4];
endfunction

produces:

test.sv:4:12: warning: invalid index 4 for 'dynamic array of int' of length 2 [-Wdynarray-index]
    return i[4];
           ^~~~
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^

-Wdynarray-range

A constant function tried to access a nonexistent range of a dynamic array.

This diagnostic is enabled by default.

Example:

typedef int ret_type[2];
localparam ret_type foo = func();
function ret_type func;
    automatic int i[] = new [2];
    return i[6:7];
endfunction

produces:

test.sv:5:12: warning: invalid range [6:7] for 'dynamic array of int' of length 2 [-Wdynarray-range]
    return i[6:7];
           ^~~~~~
test.sv:2:27: note: in call to 'func()'
localparam ret_type foo = func();
                          ^

-Welem-not-found

A constant function tried to access a nonexistent element of an associative array.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    int i[string];
    return i["Hello"];
endfunction

produces:

test.sv:4:14: warning: element "Hello" does not exist in associative array [-Welem-not-found]
    return i["Hello"];
           ~~^~~~~~~~
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^

-Wempty-body

An empty statement body for a loop or conditional statement could be confusing or misleading. If intended, move the semicolon to a separate line to suppress the warning.

This diagnostic is enabled by default.

Example:

module m;
    initial begin
        if (1); begin
        end
    end
endmodule

produces:

test.sv:3:15: warning: if statement has empty body (put the semicolon on a separate line to silence this warning) [-Wempty-body]
        if (1); begin
              ^

-Wempty-member

An unnecessary semicolon is located in a non-procedural scope (such as a module body).

Example:

module m;
    ;
endmodule

produces:

test.sv:2:5: warning: extra ';' has no effect [-Wempty-member]
    ;
    ^

-Wempty-pattern

Issued for empty assignment pattern literals, which are not allowed by SystemVerilog but are supported by some tools.

Example:

int foo[] = '{};

produces:

test.sv:1:13: warning: empty assignment patterns are disallowed by SystemVerilog [-Wempty-pattern]
int foo[] = '{};
            ^

-Wempty-queue

A constant function tried to pop an element from an empty queue.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    automatic int i[$];
    return i.pop_back();
endfunction

produces:

test.sv:4:12: warning: pop from empty queue [-Wempty-queue]
    return i.pop_back();
           ^~~~~~~~~~
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^

-Wempty-stmt

An extra semicolon in a procedural context implies an empty statement that does nothing.

Example:

module m;
    initial begin
        ;
    end
endmodule

produces:

test.sv:3:9: warning: extra ';' has no effect [-Wempty-stmt]
        ;
        ^

-Wenum-range

An enum member is specified as a range with values that are not integer literals. The LRM does not allow other constant expressions to be used here.

This diagnostic is enabled by default.

Example:

localparam int i = 1;
typedef enum { A[i:3] } e_t;

produces:

test.sv:2:18: warning: enum element ranges must be integer literals [-Wenum-range]
typedef enum { A[i:3] } e_t;
                 ^

-Wevent-const

An event expression is a constant and so will never change.

Example:

module m;
    always @(1) begin
    end
endmodule

produces:

test.sv:2:14: warning: edge expression is constant [-Wevent-const]
    always @(1) begin
             ^

-Wexpected-diag-arg

Issued for a pragma diagnostic directive that is missing an argument.

This diagnostic is enabled by default.

Example:

`pragma diagnostic

produces:

test.sv:1:19: warning: expected diagnostic pragma argument [-Wexpected-diag-arg]
`pragma diagnostic
                  ^

-Wexpected-protect-arg

An invalid argument is passed to a `pragma protect keyword expecting a string value.

This diagnostic is enabled by default.

Example:

`pragma protect author=3

produces:

test.sv:1:24: warning: 'author' pragma expects a single string argument [-Wexpected-protect-arg]
`pragma protect author=3
                       ^

-Wexpected-protect-keyword

A `pragma protect directive is missing the protect keyword to set.

This diagnostic is enabled by default.

Example:

`pragma protect

produces:

test.sv:1:16: warning: expected pragma protect keyword [-Wexpected-protect-keyword]
`pragma protect
               ^

-Wexplicit-static

static variables declared locally to a procedural block that contain an initializer require that the 'static' keyword be explicitly provided (and not just inferred from context) to clarify that the initialization happens only once. Most tools don't enforce this rule, so this is just a warning instead of an error.

This diagnostic is enabled by default.

Example:

module m;
    initial begin
        int i = 1;
    end
endmodule

produces:

test.sv:3:13: warning: initializing a static variable in a procedural context requires an explicit 'static' keyword [-Wexplicit-static]
        int i = 1;
            ^

-Wextra

Controls -Wempty-member, -Wempty-stmt, -Wdup-import, -Wpointless-void-cast, -Wcase-gen-none, -Wcase-gen-dup, -Wunused-result, -Wformat-real, -Wignored-slice, -Wtask-ignored, -Wwidth-trunc, -Wdup-attr, -Wevent-const, -Wineffective-sign, -Wport-width-trunc, -Wconstant-conversion, -Wfloat-bool-conv, -Wint-bool-conv, -Wuseless-cast, -Wunsigned-arith-shift, -Wstatic-init-order, -Wstatic-init-value, -Wfloat-int-conv, -Wfloat-narrow, -Wbitwise-rel-precedence, -Warith-in-shift, -Wlogical-not-parentheses, -Wconsecutive-comparison, -Wcase-outside-range, -Wcase-enum, -Wcase-dup, -Wcase-overlap.

-Wextra-pragma-args

Issued for a pragma directive that specifies more arguments than expected.

This diagnostic is enabled by default.

Example:

`pragma resetall extraarg

produces:

test.sv:1:18: warning: too many arguments provided for pragma 'resetall' [-Wextra-pragma-args]
`pragma resetall extraarg
                 ^

-Wextra-protect-end

An unpair `pragma protect end or end_protected was found in the source text.

This diagnostic is enabled by default.

Example:

`pragma protect end

produces:

test.sv:1:17: warning: pragma protect 'end' seen without corresponding start of block [-Wextra-protect-end]
`pragma protect end
                ^~~

-Wfinish-num

The $finish control task accepts a "finish number" of 0, 1, or 2 as its first argument. The actual call to $finish in this case passed something other than one of those values.

This diagnostic is enabled by default.

Example:

module m;
    initial $finish("Hello");
endmodule

produces:

test.sv:2:21: warning: finish argument must have value of 0, 1, or 2 [-Wfinish-num]
    initial $finish("Hello");
                    ^~~~~~~

-Wfloat-bool-conv

A floating point value is implicitly converted to a boolean predicate (such as in an if statement or loop condition). This is not necessarily wrong but can indicate mistakes where you intended to compare the value to something.

Example:

module m;
    real r;
    initial if (r) begin end // Did you mean r != 0 or something else?
endmodule

produces:

test.sv:3:17: warning: implicit conversion from floating point type 'real' to boolean value [-Wfloat-bool-conv]
    initial if (r) begin end // Did you mean r != 0 or something else?
                ^

-Wfloat-int-conv

A floating point value (real or shortreal) is implicitly converted to an integer.

Example:

function automatic f(real r);
    int i = r;
endfunction

produces:

test.sv:2:13: warning: implicit conversion from 'real' to 'int' [-Wfloat-int-conv]
    int i = r;
          ~ ^

-Wfloat-narrow

A floating point value is implicitly converted to a narrower floating point type.

Example:

function automatic f(real r);
    shortreal s = r;
endfunction

produces:

test.sv:2:19: warning: implicit conversion narrows from 'real' to 'shortreal' [-Wfloat-narrow]
    shortreal s = r;
                ~ ^

-Wfloat-widen

A floating point value is implicitly converted to a wider floating point type.

Example:

function automatic f(shortreal s);
    real r = s;
endfunction

produces:

test.sv:2:14: warning: implicit conversion widens from 'shortreal' to 'real' [-Wfloat-widen]
    real r = s;
           ~ ^

-Wformat-multibit-strength

Formatting multibit nets with the %v specifier is not allowed in SystemVerilog but most tools allow it anyway as an extension.

Example:

module m;
    wire [3:0] w;
    initial $display("%v", w);
endmodule

produces:

test.sv:3:28: warning: formatting strength values for multi-bit nets is non-standard [-Wformat-multibit-strength]
    initial $display("%v", w);
                      ~~   ^

-Wformat-real

A string formatting function was passed a real value for an integer format specifier, which will force the value to round to an integer.

Example:

module m;
    initial $display("%d", 3.14);
endmodule

produces:

test.sv:2:28: warning: real value provided for integer format specifier '%d' [-Wformat-real]
    initial $display("%d", 3.14);
                      ~~   ^~~~

-Wignored-macro-paste

Points out macro concatenation tokens that aren't actually concatenating anything due to whitespace on either side, or tokens that can't be concatenated in the first place.

Example:

`define FOO(a) a `` +
int foo;
int bar = `FOO(foo) foo;

produces:

test.sv:3:11: warning: paste token is pointless because it is adjacent to whitespace [-Wignored-macro-paste]
int bar = `FOO(foo) foo;
          ^
test.sv:1:18: note: expanded from macro 'FOO'
`define FOO(a) a `` +
                 ^

-Wignored-slice

A streaming operator with direction left-to-right provides a slice size, which has no effect because only right-to-left streaming can use a slice size.

Example:

int a;
int b = {>> 4 {a}};

produces:

test.sv:2:13: warning: slice size ignored for left-to-right streaming operator [-Wignored-slice]
int b = {>> 4 {a}};
            ^

-Wimplicit-conv

An implicit conversion in an expression converts between two unrelated types. SystemVerilog allows this for all packed integral types but it often indicates a mistake in the code.

This diagnostic is enabled by default.

Example:

module m;
    struct packed { logic a; int b; } foo;
    union packed { int a; int b; } bar;
    initial foo = bar;
endmodule

produces:

test.sv:4:19: warning: implicit conversion from '<unnamed packed union>' to '<unnamed packed struct>' [-Wimplicit-conv]
    initial foo = bar;
                ~ ^~~

-Wimplicit-net-port

A net port that elides its net type occurs in a context where ‘default_nettype is set to 'none’. This technically should be an error but it makes the use of 'none' as a default nettype very annoying and most tools just default to a wire in this case.

Example:

`default_nettype none

module m(input i);
endmodule

produces:

test.sv:3:16: warning: implicit net port disallowed because `default_nettype is set to 'none' [-Wimplicit-net-port]
module m(input i);
               ^

-Wimplicit-port-type-mismatch

An implicit named port connection is made between two inequivalent types. Unlike with a normal port connection, where the type of the connection undergoes implicit conversion, the LRM specifies that this case is an error. slang makes this an error by default but it can be turned into a warning, to support code compatibility with commercial tools.

This diagnostic is enabled by default.

Example:

module m(logic p);
endmodule

module n;
    int p;
    m m1(.p);
endmodule

produces:

test.sv:6:11: warning: implicit named port 'p' of type 'logic' connects to value of inequivalent type 'int' [-Wimplicit-port-type-mismatch]
    m m1(.p);
          ^
test.sv:6:11: error: 'p' cannot be connected to 'inout' port (only nets are allowed)
    m m1(.p);
          ^
test.sv:5:9: note: declared here
    int p;
        ^

-Windex-oob

An out-of-bounds value was used to index an array. This is an error by default but can be downgraded to a warning for compatibility with other tools.

This diagnostic is enabled by default.

Example:

logic [7:0] a;
logic b = a[9];

produces:

test.sv:2:13: warning: cannot refer to element 9 of 'logic[7:0]' [-Windex-oob]
logic b = a[9];
            ^

-Wineffective-sign

For a non-ANSI instance port or function body port declaration, the port I/O specifies a signing keyword but the actual data type of the port does not permit that signing to take effect.

Example:

module m(a);
    input unsigned a;
    int a;
endmodule

produces:

test.sv:2:11: warning: 'unsigned' on I/O declaration has no effect on type 'int' [-Wineffective-sign]
    input unsigned a;
          ^~~~~~~~
test.sv:3:9: note: declared here
    int a;
        ^

-Wint-bool-conv

A multi-bit integer value is implicitly converted to a boolean predicate (such as in an if statement or loop condition). This is not necessarily wrong but can indicate mistakes where you intended to compare the value to something.

Example:

module m;
    int i;
    initial if (i + 2) begin end // Did you mean i + 2 != 0 or something else?
endmodule

produces:

test.sv:3:17: warning: implicit conversion from 'int' to boolean value [-Wint-bool-conv]
    initial if (i + 2) begin end // Did you mean i + 2 != 0 or something else?
                ^~~~~

-Wint-float-conv

A integer value is implicitly converted to a floating point type (real or shortreal).

Example:

function automatic f(int i);
    real r = i;
endfunction

produces:

test.sv:2:14: warning: implicit conversion from 'int' to 'real' [-Wint-float-conv]
    real r = i;
           ~ ^

-Wint-overflow

Issued for integer literals that overflow a 32-bit integer (31-bits plus sign).

This diagnostic is enabled by default.

Example:

int i = 2147483648;

produces:

test.sv:1:9: warning: signed integer literal overflows 32 bits, will be truncated to -2147483648 [-Wint-overflow]
int i = 2147483648;
        ^

-Winvalid-encoding-byte

A character in an encoded protected envelope is invalid for the kind of encoding specified. The rest of the protected envelope will be skipped by searching for an end pragma.

This diagnostic is enabled by default.

Example:

`pragma protect begin_protected
`pragma protect encoding=(enctype="base64"), data_block
asdf()0123
`pragma protect end_protected

produces:

test.sv:3:5: warning: invalid base64 byte '(' -- attempting to skip remaining encoded text [-Winvalid-encoding-byte]
asdf()0123
    ^

-Winvalid-pragma-number

A `pragma protect option expected a valid 32-bit integer value but received something else instead.

This diagnostic is enabled by default.

Example:

`pragma protect encoding=(enctype="base64", line_length="hello")

produces:

test.sv:1:57: warning: expected a 32-bit integer value for pragma option [-Winvalid-pragma-number]
`pragma protect encoding=(enctype="base64", line_length="hello")
                                                        ^~~~~~~

-Winvalid-pragma-viewport

A `pragma protect viewport directive was given invalid options. All such directives must be of the form (object = <string>, access = <string>)

This diagnostic is enabled by default.

Example:

`pragma protect viewport=(not_object = "hello")

produces:

test.sv:1:26: warning: pragma protect viewport requires options to be specified in the form (object = <string>, access = <string>) [-Winvalid-pragma-viewport]
`pragma protect viewport=(not_object = "hello")
                         ^~~~~~~~~~~~~~~~~~~~~~

-Winvalid-pulsestyle

A pulsestyle or showcancelled declaration targets an output terminal that has previously been used in a timing path declaration, which is not allowed according to the LRM.

This diagnostic is enabled by default.

Example:

module m(input a, output b);
    specify
        (a => b) = 1;
        pulsestyle_ondetect b;
    endspecify
endmodule

produces:

test.sv:4:29: warning: invalid use of pulsestyle_ondetect for 'b' since it has previously appeared in a path declaration [-Winvalid-pulsestyle]
        pulsestyle_ondetect b;
                            ^
test.sv:3:15: note: declared here
        (a => b) = 1;
              ^

-Wisunbounded-param-arg

The SystemVerilog LRM 1800-2023 requires that the argument to the $isunbounded system function be a parameter name. This seems needlessly restrictive and conflicts with the wording in prior versions so this is implemented as a pedantic warning only.

Example:

localparam p = $isunbounded(1 + 1);

produces:

test.sv:1:29: warning: argument to $isunbounded must be the name of a parameter [-Wisunbounded-param-arg]
localparam p = $isunbounded(1 + 1);
                            ^~~~~

-Wlifetime-prototype

Lifetime specifiers are not allowed on method prototype declarations but some tools allow it as an extension.

This diagnostic is enabled by default.

Example:

class C;
    extern function automatic void foo;
endclass

function automatic void C::foo;
endfunction

produces:

test.sv:2:21: warning: lifetime specifier is not allowed on prototype declaration [-Wlifetime-prototype]
    extern function automatic void foo;
                    ^~~~~~~~~

-Wlogical-not-parentheses

Identifies a logical not operator used without parentheses around the operand, followed by a comparison operator. This can indicate a mistake in the intended order of operations.

Example:

module m;
    int a, b;
    initial begin
        if (!a < b) begin end
    end
endmodule

produces:

test.sv:4:13: warning: logical not is only applied to the left hand side of this comparison [-Wlogical-not-parentheses]
        if (!a < b) begin end
            ^  ~
test.sv:4:14: note: add parentheses after the '!' to evaluate the comparison first
        if (!a < b) begin end
             ^~~~~
test.sv:4:13: note: add parentheses around left hand side expression to silence this warning
        if (!a < b) begin end
            ^~

-Wlogical-op-parentheses

Identifies a mix of logical operators with different levels of precedence without any parentheses, which can indicate a mistake in the intended order of operations.

Example:

module m;
    logic a, b, c;
    initial begin
        if (a || b && c) begin end
    end
endmodule

produces:

test.sv:4:20: warning: '&&' within '||' [-Wlogical-op-parentheses]
        if (a || b && c) begin end
              ~~ ~~^~~~
test.sv:4:20: note: place parentheses around the '&&' expression to silence this warning
        if (a || b && c) begin end
                 ~~^~~~

-Wmissing-format

A string formatting function has a lone '%' at the end of the format string, implying that the rest of the specifier is missing. If a literal '%' is intended in the output, use the standard '%%' to achieve that.

This diagnostic is enabled by default.

Example:

module m;
    initial $display("Hello World %");
endmodule

produces:

test.sv:2:35: warning: missing format specifier [-Wmissing-format]
    initial $display("Hello World %");
                                  ^

-Wmissing-top

No valid top-level modules exist in the design. No top has been instantiated.

This diagnostic is enabled by default.

Example:

module m #(parameter int i);
endmodule

produces:

warning: no top-level modules found in design [-Wmissing-top]

-Wmultibit-edge

A timing control edge expression (posedge, negedge, etc) is wider than one bit, which can indicate a mistake since only changes to the first bit will trigger the edge.

This diagnostic is enabled by default.

Example:

module m;
    int i;
    always @(posedge i) begin end
endmodule

produces:

test.sv:3:22: warning: edge of expression of type 'int' will only trigger on changes to the first bit [-Wmultibit-edge]
    always @(posedge i) begin end
                     ^

-Wnegative-timing-limit

A system timing check parameter that should be positive has a negative value.

This diagnostic is enabled by default.

Example:

module m(input a, b);
    specify
        $setup(posedge a, b, -1);
    endspecify
endmodule

produces:

test.sv:3:30: warning: timing check limit value '-1' should not be negative [-Wnegative-timing-limit]
        $setup(posedge a, b, -1);
                             ^~

-Wnested-protect-begin

Nested `pragma protect begin directives were found, which is disallowed.

This diagnostic is enabled by default.

Example:

`pragma protect begin
`pragma protect begin

produces:

test.sv:2:17: warning: nested pragma protect begin-end blocks are not allowed [-Wnested-protect-begin]
`pragma protect begin
                ^~~~~

-Wnet-inconsistent

A connection (or part of a connection) between an external net and an internal net port has inconsistent net types. The SystemVerilog LRM defines which combinations of net types are inconsistent and should produce a warning; see section [23.3.3.7] "Port connections with dissimilar net types (net and port collapsing)" for more detail.

This diagnostic is enabled by default.

Example:

module m (input .a({b, {c[1:0], d}}));
    wand b;
    wand [3:0] c;
    supply0 d;
endmodule

module top;
    wand a;
    wor b;
    trireg [1:0] c;
    m m1({a, b, c});
endmodule

produces:

test.sv:11:10: warning: net type 'wor' of connection bits [2:2] is inconsistent with net type 'wand' of corresponding port range [-Wnet-inconsistent]
    m m1({a, b, c});
         ^~~~~~~~~
test.sv:1:18: note: declared here
module m (input .a({b, {c[1:0], d}}));
                 ^
test.sv:11:10: warning: net type 'trireg' of connection bits [1:1] is inconsistent with net type 'wand' of corresponding port range [-Wnet-inconsistent]
    m m1({a, b, c});
         ^~~~~~~~~

-Wnonblocking-final

A nonblocking assignment is used in a 'final' block, which will have no effect.

This diagnostic is enabled by default.

Example:

module m;
    int i;
    final begin
        i <= 1;
    end
endmodule

produces:

test.sv:4:9: warning: nonblocking assignments in final blocks have no effect [-Wnonblocking-final]
        i <= 1;
        ^~~~~~

-Wnonstandard-dist

'dist' constraint items are technically not allowed to be surrounded by parentheses according to the language grammar, but most tools allow it as an extension.

Example:

class C;
    rand bit a;
    rand bit [3:0] b;
    constraint cmd_c {
        a -> (b dist { 0 := 1, [1:15] := 1});
    }
endclass

produces:

test.sv:5:14: warning: use of parentheses around 'dist' expression is non-standard [-Wnonstandard-dist]
        a -> (b dist { 0 := 1, [1:15] := 1});
             ^                             ~

-Wnonstandard-escape-code

Detects use of '\%' in string literals. This is not a real escape code but other tools silently allow it anyway.

Example:

string s = "Hello World\%";

produces:

test.sv:1:24: warning: non-standard character escape sequence '\%' [-Wnonstandard-escape-code]
string s = "Hello World\%";
                       ^

-Wnonstandard-foreach

foreach loops are not allowed to have multidimensional brackets when declaring loop variables, but most tools allow it as an extension.

Example:

module top;
    int array[8][8];
    initial begin
        foreach (array[i]) begin
            foreach (array[i][j]) begin
                array[i][j] = i * j;
            end
        end
    end
endmodule

produces:

test.sv:5:22: warning: non-standard foreach loop variable list [-Wnonstandard-foreach]
            foreach (array[i][j]) begin
                     ^~~~~~~~

-Wnonstandard-generate

Indicates a standalone generate block (begin / end pair) without a corresponding generate loop or condition. This was allowed in older Verilog standards but is no longer allowed in SystemVerilog.

Example:

module m;
    begin : gen_block
        int i = 1;
    end
endmodule

produces:

test.sv:2:5: warning: standalone generate block without loop or condition is not allowed in SystemVerilog [-Wnonstandard-generate]
    begin : gen_block
    ^

-Wnonstandard-sys-func

Indicates a call to a nonstandard system function. Currently this only applies to the $psprintf function, which is a synonym for $sformatf.

Example:

module m;
    initial $psprintf("%d", 42);
endmodule

produces:

test.sv:2:13: warning: system function '$psprintf' is non-standard [-Wnonstandard-sys-func]
    initial $psprintf("%d", 42);
            ^~~~~~~~~~~~~~~~~~~

-Wpacked-array-conv

Indicates an implicit conversion between types with differing packed array dimensions, even if their overall bit width is the same. This will not warn for types with a single packed dimension; at least one of the types must have multiple declared dimensions.

Example:

module m;
    logic [3:1][1:0] a;
    logic [5:0][1:0] b;
    initial b = a;
endmodule

produces:

test.sv:4:17: warning: implicit conversion from 'logic[3:1][1:0]' to 'logic[5:0][1:0]' [-Wpacked-array-conv]
    initial b = a;
              ~ ^

-Wparentheses

Controls -Wbitwise-rel-precedence, -Warith-in-shift, -Wlogical-not-parentheses, -Wbitwise-op-parentheses, -Wlogical-op-parentheses, -Wconditional-precedence, -Wconsecutive-comparison.

-Wpedantic

Controls -Wempty-pattern, -Wimplicit-net-port, -Wnonstandard-escape-code, -Wnonstandard-generate, -Wformat-multibit-strength, -Wnonstandard-sys-func, -Wnonstandard-foreach, -Wnonstandard-dist, -Wisunbounded-param-arg, -Wudp-coverage.

-Wpointless-void-cast

A function call is cast to 'void' but it already returns void so the cast is pointless.

Example:

module m;
    function void foo; endfunction
    initial begin
        void'(foo());
    end
endmodule

produces:

test.sv:4:15: warning: cast to void for void-returning function 'foo' has no effect [-Wpointless-void-cast]
        void'(foo());
              ^~~~~

-Wport-coercion

An input net port has been coerced to 'inout' direction because it is assigned to in the instance body. Alternatively, an output net port has been coerced to 'inout' direction because it is assigned externally to the instance.

This diagnostic is enabled by default.

Example:

module m(input wire a, output b);
    assign a = 1;
endmodule

module n;
    wire b;
    m m1(1, b);
    assign b = 1;
endmodule

produces:

test.sv:2:12: warning: input net port 'a' coerced to 'inout' [-Wport-coercion]
    assign a = 1;
           ^
test.sv:1:21: note: declared here
module m(input wire a, output b);
                    ^
test.sv:7:13: warning: output net port 'b' coerced to 'inout' [-Wport-coercion]
    m m1(1, b);
            ^
test.sv:8:12: note: driven here
    assign b = 1;
           ^

-Wport-width-expand

An implicit conversion in a port connection expression expands a type. This may be harmless, but the warning provides a mechanism for discovering unintended conversions. An explicit cast can be used to silence the warning.

Example:

module m(input int a); endmodule

module n;
    logic [1:0] a;
    m m1(.a(a));
endmodule

produces:

test.sv:5:13: warning: implicit conversion of port connection expands from 2 to 32 bits [-Wport-width-expand]
    m m1(.a(a));
            ^

-Wport-width-trunc

An implicit conversion in a port connection expression truncates a type. This conversion potentially loses data. An explicit cast can be used to silence the warning.

Example:

module m(input logic [1:0] a); endmodule

module n;
    int a;
    m m1(.a(a));
endmodule

produces:

test.sv:5:13: warning: implicit conversion of port connection truncates from 32 to 2 bits [-Wport-width-trunc]
    m m1(.a(a));
            ^

-Wpragma-diag-level

Issued for a malformed diagnostic pragma. A severity code was expected where the given location is indicated.

This diagnostic is enabled by default.

Example:

`pragma diagnostic foo=3'd3

produces:

test.sv:1:20: warning: expected diagnostic severity (ignore,warn,error,fatal) [-Wpragma-diag-level]
`pragma diagnostic foo=3'd3
                   ^~~

-Wprotect-arglist

A `pragma protect keyword expected a list of key=value options but did not receive them.

This diagnostic is enabled by default.

Example:

`pragma protect encoding=3

produces:

test.sv:1:26: warning: protect encoding directive expects a parenthesized list of key=value options [-Wprotect-arglist]
`pragma protect encoding=3
                         ^

-Wprotect-encoding-bytes

An encoded block in a protected envelope differed in size from what was specified in a prior encoding pragma directive.

This diagnostic is enabled by default.

Example:

`pragma protect begin_protected
`pragma protect encoding=(enctype="base64", bytes=6), data_public_key
asdfas==
`pragma protect end_protected

produces:

test.sv:3:8: warning: 4 bytes decoded in protected envelope but encoding pragma said to expect 6 [-Wprotect-encoding-bytes]
asdfas==
       ^

-Wprotected-envelope

Any use of a pragma protect region in the source will trigger this warning, as slang is unable to actually decrypt the contents of that region (it is assumed that no IP vendor would be willing to share decryption keys with an open source tool anyway). The text will be decoded and skipped in its entirety, which may or may not result in a valid design.

This diagnostic is enabled by default.

Example:

`pragma protect begin_protected
`pragma protect encoding=(enctype="raw"), data_block
asdfasdf
`pragma protect end_protected

produces:

test.sv:3:1: warning: protected envelopes cannot be decrypted and will be skipped entirely [-Wprotected-envelope]
asdfasdf
^

-Wqueue-range

A constant function is accessing a queue with a reversed range, which is defined to always yield an empty queue.

This diagnostic is enabled by default.

Example:

typedef int ret_type[$];
localparam ret_type foo = func();
function ret_type func;
    automatic int i[$] = {1, 2, 3};
    return i[2:0];
endfunction

produces:

test.sv:5:12: warning: reversed selection range [2:0] for queue will always yield an empty result [-Wqueue-range]
    return i[2:0];
           ^~~~~~
test.sv:2:27: note: in call to 'func()'
localparam ret_type foo = func();
                          ^

-Wrange-oob

An out-of-bounds range was used to select from an array. This is an error by default but can be downgraded to a warning for compatibility with other tools.

This diagnostic is enabled by default.

Example:

logic [7:0] a;
logic [2:0] b = a[9:7];

produces:

test.sv:2:19: warning: cannot select range of [9:7] from 'logic[7:0]' [-Wrange-oob]
logic [2:0] b = a[9:7];
                  ^~~

-Wrange-width-oob

An indexed part-select has a width that is wider than the bounds of the array it is selecting. This is an error by default but can be downgraded to a warning for compatibility with other tools.

This diagnostic is enabled by default.

Example:

logic [1:0] a;
int b;
logic [2:0] c = a[b+:3];

produces:

test.sv:3:22: warning: cannot select range of 3 elements from 'logic[1:0]' [-Wrange-width-oob]
logic [2:0] c = a[b+:3];
                     ^

-Wraw-protect-eof

A "raw" encoded protected envelope did not terminate before the end of the source file.

This diagnostic is enabled by default.

Example:

`pragma protect encoding=(enctype="raw"), data_block
asdfasdf

produces:

test.sv:2:8: warning: reached end of file while processing 'raw' encoded protected envelope [-Wraw-protect-eof]
asdfasdf
       ^

-Wreal-overflow

Issued for real literals that are too large to be represented.

This diagnostic is enabled by default.

Example:

real r = 1.79769e+309;

produces:

test.sv:1:10: warning: value of real literal is too large; maximum is 1.79769e+308 [-Wreal-overflow]
real r = 1.79769e+309;
         ^

-Wreal-underflow

Issued for real literals that are too small to be represented.

This diagnostic is enabled by default.

Example:

real r = 4.94066e-325;

produces:

test.sv:1:10: warning: value of real literal is too small; minimum is 4.94066e-324 [-Wreal-underflow]
real r = 4.94066e-325;
         ^

-Wredef-macro

Issued for redefining a macro name with a different body.

This diagnostic is enabled by default.

Example:

`define FOO 1
`define FOO 2

produces:

test.sv:2:9: warning: macro 'FOO' redefined [-Wredef-macro]
`define FOO 2
        ^~~
test.sv:1:9: note: previous definition here
`define FOO 1
        ^

-Wreversed-range

An open range with constant bounds is reversed (i.e. has a larger left-hand side compared to its right). Such a range will behave as if it's empty and therefore never be selected.

This diagnostic is enabled by default.

Example:

class C;
    rand bit [4:0] a;
    constraint a_c {
        a dist { 16 :/ 1, [15:1] :/ 1};
    }
endclass

produces:

test.sv:4:27: warning: reversed range will behave as if it were empty [-Wreversed-range]
        a dist { 16 :/ 1, [15:1] :/ 1};
                          ^~~~~~

-Wseq-no-match

Warns about a sequence expression that can never be matched.

This diagnostic is enabled by default.

Example:

module top;
    assert property ((1'b1 ##1 1'b0) intersect (1'b1[*0] ##2 1'b1));
endmodule

produces:

test.sv:2:22: warning: sequence can never be matched [-Wseq-no-match]
    assert property ((1'b1 ##1 1'b0) intersect (1'b1[*0] ##2 1'b1));
                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
test.sv:2:32: note: expression is always false
    assert property ((1'b1 ##1 1'b0) intersect (1'b1[*0] ##2 1'b1));
                               ^~~~

-Wsign-compare

A comparison operator has operands of differing signs. The signed operand will be treated as unsigned, which can lead to unexpected results.

Example:

module m;
    int a = -1;
    int unsigned b = 1;
    initial begin
        if (a < b) begin
        end
    end
endmodule

produces:

test.sv:5:15: warning: comparison of differently signed types ('int' and 'int unsigned') [-Wsign-compare]
        if (a < b) begin
            ~ ^ ~

-Wsign-conversion

An implicit conversion changes the signedness of an integer type (from signed to unsigned or vice versa).

Example:

module m;
    logic signed [31:0] a;
    logic [31:0] b;
    assign b = a;
endmodule

produces:

test.sv:4:16: warning: implicit conversion changes signedness from 'logic signed[31:0]' to 'logic[31:0]' [-Wsign-conversion]
    assign b = a;
             ~ ^

-Wspecify-condition-expr

State-dependent path conditions in specify blocks are restricted to a subset of expression types and operators (see Table 30-1 in the LRM for the list of valid operators). This is an error by default but can be downgraded to a warning for compatibility with other tools.

This diagnostic is enabled by default.

Example:

module m(input b, output c);
    wire integer a;
    specify
        if (a === 1 + 1) (b => c) = (0,0);
    endspecify
endmodule

produces:

test.sv:4:19: warning: expression is not valid in a state-dependent path condition [-Wspecify-condition-expr]
        if (a === 1 + 1) (b => c) = (0,0);
                  ^~~~~

-Wspecify-param

The LRM disallows using parameters inside of specify blocks. Most tools allow this with a warning so slang makes it a warning as well.

This diagnostic is enabled by default.

Example:

module m(input [1:0] a, output [1:0] b);
    parameter p = 1;
    specify
        (a[p] => b[0]) = 1;
    endspecify
endmodule

produces:

test.sv:4:12: warning: parameters cannot be used in specify blocks [-Wspecify-param]
        (a[p] => b[0]) = 1;
           ^

-Wsplit-distweight-op

Some tools allow the dist weight operators to be split instead of a single token. slang will issue this warning as an error by default but it can be downgraded for compatibility.

This diagnostic is enabled by default.

Example:

class c;
  rand int val;
  constraint cst_sum {
    val dist {1 :    = 10, 4 :   / 20};
  }
endclass

produces:

test.sv:4:17: warning: split dist weight operator is not allowed; SystemVerilog requires that they be joined together [-Wsplit-distweight-op]
    val dist {1 :    = 10, 4 :   / 20};
                ^    ~
test.sv:4:30: warning: split dist weight operator is not allowed; SystemVerilog requires that they be joined together [-Wsplit-distweight-op]
    val dist {1 :    = 10, 4 :   / 20};
                             ^   ~

-Wstatic-init-order

A static variable's initializer refers to another variable that does not have a defined order of initialization relative to the first. This means that the initialization may or may not work as expected depending on how the tool chooses to schedule the initializers.

Example:

package p;
    int i = 1;
endpackage

module m;
    import p::i;
    int j = i;
endmodule

produces:

test.sv:7:13: warning: initializer for static variable 'j' refers to another static variable 'i' which will be initialized in an indeterminate order [-Wstatic-init-order]
    int j = i;
            ^
test.sv:2:9: note: declared here
    int i = 1;
        ^

-Wstatic-init-value

A static variable's initializer expression refers to an uninitialized variable, a net, a port, or a modport member, which won't have a value assigned by the time the initializer runs. The variable therefore will always be initialized to the default value.

Example:

module m(input i);
    logic j = i;
endmodule

produces:

test.sv:2:15: warning: initializer for static variable 'j' refers to 'i' which will not have a value at initialization time [-Wstatic-init-value]
    logic j = i;
              ^
test.sv:1:16: note: declared here
module m(input i);
               ^

-Wstatic-skipped

A constant function contains a static variable with an initializer. That initializer will be skipped during constant evaluation, which could lead to unintuitive results.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    static int i = 1;
    return i;
endfunction

produces:

test.sv:3:20: warning: static variable initialization is skipped in constant function calls [-Wstatic-skipped]
    static int i = 1;
                   ^
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^

-Wtask-ignored

A constant function contains a system task invocation which will be skipped during constant evaluation. This could yield unintuitive results.

Example:

localparam string foo = func();
function string func;
    automatic string s;
    $swrite(s, "asdf %d", 3);
    return s;
endfunction

produces:

test.sv:4:5: warning: system task '$swrite' is ignored in constant expression [-Wtask-ignored]
    $swrite(s, "asdf %d", 3);
    ^~~~~~~~~~~~~~~~~~~~~~~~
test.sv:1:25: note: in call to 'func()'
localparam string foo = func();
                        ^

-Wudp-coverage

A user-defined primitive is edge sensitive but does not provide an output value for all possible edges of all inputs. This is not necessarily wrong; the default output value when given unspecified input combinations is 'x', but the LRM mentions this constraint in section 29.6 so this warning can be used if you wish to be pedantic. Additionally, it can be useful for checking for missed transitions when developing and simulating the behavioral model of industrial cells, which are commonly implemented as Verilog primitives.

Example:

primitive d_edge_ff (q, clock, data);
    output q; reg q;
    input clock, data;
    table
        // clock data q q+
        // obtain output on rising edge of clock
        (01) 0 : ? : 0 ;
        (01) 1 : ? : 1 ;
        (0?) 1 : 1 : 1 ;
        (0?) 0 : 0 : 0 ;
        // ignore negative edge of clock
        (?0) ? : ? : - ;
        // missed clock edge (1x) specification
        // missed edge specifications for data signal
    endtable
endprimitive

produces:

test.sv:1:11: warning: primitive does not specify outputs for all edges of all inputs [-Wudp-coverage]
primitive d_edge_ff (q, clock, data);
          ^
note: missed desired output for rows:
(1x) 0 
(x1) 0 
(1x) 1 
(x1) 1 
(01) x 
(0x) x 
(1x) x 
(x1) x 
...and more

-Wudp-port-empty

A connection to a user-defined primitive instance is an empty expression. While allowed, this is easily confused with a misplaced comma and is likely not what you want.

This diagnostic is enabled by default.

Example:

primitive p1 (output a, input b);
    table 00:0; endtable
endprimitive

module m;
    logic a;
    p1 (a,);
endmodule

produces:

test.sv:2:11: error: incorrect number of input fields in table row; have 2 but expect 1
    table 00:0; endtable
          ^~
test.sv:7:11: warning: primitive port connection is empty [-Wudp-port-empty]
    p1 (a,);
          ^

-Wunassigned-variable

A variable is used but never has a value assigned.

A variable with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular variable.

Example:

module m;
    int i;
    int j = i;
endmodule

produces:

test.sv:2:9: warning: variable 'i' is never assigned a value [-Wunassigned-variable]
    int i;
        ^

-Wunconnected-port

An instance port was left unconnected and it has no default value.

This diagnostic is enabled by default.

Example:

module m(input int i);
endmodule

module n;
    m m1();
endmodule

produces:

test.sv:5:7: warning: port 'i' has no connection [-Wunconnected-port]
    m m1();
      ^

-Wunconnected-unnamed-port

An unnamed instance port was left unconnected.

This diagnostic is enabled by default.

Example:

module m({a, b});
    input a, b;
endmodule

module n;
    m m1();
endmodule

produces:

test.sv:6:7: warning: instance does not provide a connection for an unnamed port [-Wunconnected-unnamed-port]
    m m1();
      ^
test.sv:1:10: note: declared here
module m({a, b});
         ^

-Wundriven-net

A net is used but never has a value driven.

A net with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular net.

Example:

module m(output x);
    wire w;
    assign x = w;
endmodule

produces:

test.sv:2:10: warning: net 'w' is never driven [-Wundriven-net]
    wire w;
         ^

-Wundriven-port

An output port signal is never given a value.

A port with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular port.

Example:

module m(output x);
endmodule

produces:

test.sv:1:17: warning: undriven output port 'x' [-Wundriven-port]
module m(output x);
                ^

-Wunknown-diag-arg

Issued for an unknown argument given to a pragma diagnostic directive.

This diagnostic is enabled by default.

Example:

`pragma diagnostic pushh

produces:

test.sv:1:20: warning: unknown diagnostic pragma argument 'pushh' [-Wunknown-diag-arg]
`pragma diagnostic pushh
                   ^~~~~

-Wunknown-escape-code

Detects use of unknown character escape codes in string literals.

This diagnostic is enabled by default.

Example:

string s = "Hello World\q";

produces:

test.sv:1:24: warning: unknown character escape sequence '\q' [-Wunknown-escape-code]
string s = "Hello World\q";
                       ^

-Wunknown-library

A configuration library list references an unknown library.

This diagnostic is enabled by default.

Example:

config cfg;
    design d;
    default liblist foo;
endconfig

produces:

test.sv:2:12: error: 'd' is not a valid top-level module
    design d;
           ^
test.sv:3:21: warning: unknown library 'foo' [-Wunknown-library]
    default liblist foo;
                    ^~~

-Wunknown-pragma

Issued for an unknown pragma directive.

This diagnostic is enabled by default.

Example:

`pragma foo

produces:

test.sv:1:9: warning: unknown pragma 'foo' [-Wunknown-pragma]
`pragma foo
        ^~~

-Wunknown-protect-encoding

The specified encoding name in a `pragma protect encoding directive is not known or supported. slang will try to work with the encoded data as though it were raw, which may or may not parse correctly depending on how the actual encoding functions.

This diagnostic is enabled by default.

Example:

`pragma protect encoding=(enctype="foobar")

produces:

test.sv:1:35: warning: unknown protect encoding 'foobar', treating as 'raw' -- source text may not be processed correctly [-Wunknown-protect-encoding]
`pragma protect encoding=(enctype="foobar")
                                  ^~~~~~~~

-Wunknown-protect-keyword

A `pragma protect directive specified an unknown keyword.

This diagnostic is enabled by default.

Example:

`pragma protect foobar

produces:

test.sv:1:17: warning: unknown pragma protect keyword 'foobar' [-Wunknown-protect-keyword]
`pragma protect foobar
                ^~~~~~

-Wunknown-protect-option

An unknown key=value option was passed to a `pragma protect keyword.

This diagnostic is enabled by default.

Example:

`pragma protect encoding=(enctype="base64", foo="bar")

produces:

test.sv:1:45: warning: unknown protect encoding option 'foo' [-Wunknown-protect-option]
`pragma protect encoding=(enctype="base64", foo="bar")
                                            ^~~

-Wunknown-sys-name

An unknown system task or function is called. This is an error by default but can be downgraded to allow analyzing code using special system names defined by other tools.

This diagnostic is enabled by default.

Example:

module m;
    always_comb begin
        if (!$somename) begin end
    end
endmodule

produces:

test.sv:3:14: warning: unknown system name '$somename' [-Wunknown-sys-name]
        if (!$somename) begin end
             ^~~~~~~~~

-Wunsigned-arith-shift

An arithmetic right shift of an unsigned integral type will always shift in zeros, which can be confusing since typically this operator is used to shift in the value of the most significant bit. If this is intended behavior use the logical right shift operator which does the same.

Example:

function bit[31:0] f1(int unsigned i);
    return i >>> 5;
endfunction

produces:

test.sv:2:12: warning: arithmetic right shift of unsigned type 'int unsigned' will always shift in zeros (use logical shift if that is intended) [-Wunsigned-arith-shift]
    return i >>> 5;
           ^

-Wunsized-concat

An unsized type is used in a concatenation. This is not allowed in SystemVerilog but most tools allow it anyway as an extension.

This diagnostic is enabled by default.

Example:

longint i = {1, 2};

produces:

test.sv:1:14: warning: unsized integer in concat; using a width of 32 [-Wunsized-concat]
longint i = {1, 2};
             ^

-Wunused

Controls -Wunused-def, -Wunused-net, -Wunused-implicit-net, -Wunused-variable, -Wundriven-net, -Wunassigned-variable, -Wunused-but-set-net, -Wunused-but-set-variable, -Wunused-port, -Wundriven-port, -Wunused-argument, -Wunused-parameter, -Wunused-type-parameter, -Wunused-typedef, -Wunused-genvar, -Wunused-assertion-decl, -Wunused-but-set-port, -Wunused-config-cell, -Wunused-config-instance, -Wunused-import, -Wunused-wildcard-import.

-Wunused-argument

A task or function formal argument is not used in its body.

An argument with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular argument.

Example:

function foo(int x);
endfunction

produces:

test.sv:1:18: warning: unused formal argument 'x' [-Wunused-argument]
function foo(int x);
                 ^

-Wunused-assertion-decl

An assertion declaration (sequence, property, or let) is never used.

A declaration with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular declaration.

Example:

module m;
    sequence s;
        1;
    endsequence
endmodule

produces:

test.sv:2:14: warning: unused sequence 's' [-Wunused-assertion-decl]
    sequence s;
             ^

-Wunused-but-set-net

A net has a value driven but that value is never used.

A net with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular net.

Example:

module m;
    wire x;
    assign x = 1;
endmodule

produces:

test.sv:2:10: warning: net 'x' is driven but its value is never used [-Wunused-but-set-net]
    wire x;
         ^

-Wunused-but-set-port

A port has a value assigned but that value is never used. This only applies to 'inout' ports. The assumption is that if the port doesn't need to be read, the direction should be changed to 'output' instead.

A port with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular port.

Example:

module m(inout x);
    assign x = 1;
endmodule

produces:

test.sv:1:16: warning: 'inout' port 'x' is driven but its value is never used [-Wunused-but-set-port]
module m(inout x);
               ^

-Wunused-but-set-variable

A variable has a value assigned but that value is never used.

A variable with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular variable.

Example:

module m;
    int i;
    initial i = 42;
endmodule

produces:

test.sv:2:9: warning: variable 'i' is assigned but its value is never used [-Wunused-but-set-variable]
    int i;
        ^

-Wunused-config-cell

A configuration cell rule is unused, which may mean that there's a typo in the target name.

This diagnostic is enabled by default.

Example:

config cfg;
    design top;
    cell foo liblist l;
endconfig

module top;
endmodule

produces:

test.sv:3:5: warning: unused cell config rule [-Wunused-config-cell]
    cell foo liblist l;
    ^~~~~~~~~~~~~~~~~~~

-Wunused-config-instance

A configuration instance rule is unused, which means that target path does not exist in the design.

This diagnostic is enabled by default.

Example:

config cfg;
    design top;
    instance top.foo liblist l;
endconfig

module top;
endmodule

produces:

test.sv:3:5: warning: unused config rule -- instance path does not exist in the design [-Wunused-config-instance]
    instance top.foo liblist l;
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~

-Wunused-def

A module, interface, or program definition is unused in the design.

A definition with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular definition.

Example:

module m #(parameter int i);
endmodule

module top;
endmodule

produces:

test.sv:1:8: warning: module definition is unused [-Wunused-def]
module m #(parameter int i);
       ^

-Wunused-genvar

A genvar is never used.

A genvar with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular genvar.

Example:

module m;
    genvar g;
endmodule

produces:

test.sv:2:12: warning: unused genvar 'g' [-Wunused-genvar]
    genvar g;
           ^

-Wunused-implicit-net

An implicitly created net is not referenced elsewhere in the design. This is often a typo in the name and not intentional.

A net with name '_' will never warn.

Example:

module m(output x);
    assign x = 1;
endmodule

module n;
    logic typo;
    m m1(typa);
endmodule

produces:

test.sv:7:10: warning: implicit net 'typa' is unused elsewhere [-Wunused-implicit-net]
    m m1(typa);
         ^

-Wunused-import

A package import directive is never used.

Example:

package p;
    int a;
endpackage

module m;
    import p::a;
endmodule

produces:

test.sv:6:15: warning: unused import 'a' [-Wunused-import]
    import p::a;
              ^

-Wunused-net

A net is declared but never used.

A net with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular net.

Example:

module m;
    wire w;
endmodule

produces:

test.sv:2:10: warning: unused net 'w' [-Wunused-net]
    wire w;
         ^

-Wunused-parameter

A parameter's value is never used.

A parameter with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular parameter.

Example:

module m #(parameter p = 1);
endmodule

produces:

test.sv:1:22: warning: unused parameter 'p' [-Wunused-parameter]
module m #(parameter p = 1);
                     ^

-Wunused-port

An input port signal is never used internally to the module.

A port with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular port.

Example:

module m(input x);
endmodule

produces:

test.sv:1:16: warning: unused port signal 'x' [-Wunused-port]
module m(input x);
               ^

-Wunused-result

A non-void function is invoked without inspecting its return value. Capture the result or cast the call to 'void' to suppress the warning.

Example:

module m;
    function int foo; return 1; endfunction
    initial begin
        foo();
    end
endmodule

produces:

test.sv:4:9: warning: ignoring return value of 'foo', cast to void to suppress [-Wunused-result]
        foo();
        ^~~~~

-Wunused-type-parameter

A type parameter is never used.

A parameter with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular parameter.

Example:

module m #(parameter type t = int);
endmodule

produces:

test.sv:1:27: warning: unused type parameter 't' [-Wunused-type-parameter]
module m #(parameter type t = int);
                          ^

-Wunused-typedef

A typedef is never used.

A typedef with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular typedef.

Example:

module m;
    typedef struct { int a; } foo_t;
endmodule

produces:

test.sv:2:31: warning: unused typedef 'foo_t' [-Wunused-typedef]
    typedef struct { int a; } foo_t;
                              ^

-Wunused-variable

A variable is declared but never used.

A variable with name '_' will never warn. Attributes (* unused *) or (* maybe_unused *) may be applied to suppress this warning for a particular variable.

Example:

module m;
    int i;
endmodule

produces:

test.sv:2:9: warning: unused variable 'i' [-Wunused-variable]
    int i;
        ^

-Wunused-wildcard-import

A wildcard package import directive is never used.

Example:

package p;
    int a;
endpackage

module m;
    import p::*;
endmodule

produces:

test.sv:6:15: warning: unused wildcard import [-Wunused-wildcard-import]
    import p::*;
              ^

-Wuseless-cast

An explicit cast converts an expression to the same type, so the cast does nothing.

Example:

module m;
    int i, j;
    assign i = int'(j);
endmodule

produces:

test.sv:3:19: warning: useless cast from 'int' to the same type [-Wuseless-cast]
    assign i = int'(j);
               ~~~^ ~

-Wvector-overflow

Issued for vector literals that are larger than their specified number of bits.

This diagnostic is enabled by default.

Example:

logic [7:0] i = 7'd256;

produces:

test.sv:1:20: warning: vector literal too large for the given number of bits (9 bits needed) [-Wvector-overflow]
logic [7:0] i = 7'd256;
                   ^

-Wwarning-task

A $warning elaboration task was encountered. Its message is printed by this diagnostic.

This diagnostic is enabled by default.

Example:

$warning("Hello World!");

produces:

test.sv:1:1: warning: $warning encountered: Hello World! [-Wwarning-task]
$warning("Hello World!");
^

-Wwidth-expand

An implicit conversion in an expression expands a type. This may be harmless, but the warning provides a mechanism for discovering unintended conversions. An explicit cast can be used to silence the warning.

Example:

logic [1:0] a;
int b = a;

produces:

test.sv:2:9: warning: implicit conversion expands from 2 to 32 bits [-Wwidth-expand]
int b = a;
      ~ ^

-Wwidth-trunc

An implicit conversion in an expression truncates a type. This conversion potentially loses data. An explicit cast can be used to silence the warning.

Example:

int a;
logic [1:0] b = a;

produces:

test.sv:2:17: warning: implicit conversion truncates from 32 to 2 bits [-Wwidth-trunc]
logic [1:0] b = a;
              ~ ^