Warning Reference

Reference information about all supported warnings.

Warnings

-Wcase-gen-dup

More than one case generate item was found to have the same value. The second case block will never be selected.

Example:

module m;
    case (1)
        1: begin end
        1: begin end
    endcase
endmodule

produces:

test.sv:4:9: warning: more than one case generate block matches the value 1 [-Wcase-gen-dup]
        1: begin end
        ^
test.sv:3:9: note: previous match here
        1: begin end
        ^


-Wcase-gen-none

A case generate directive did not match any items and so no block was selected.

Example:

module m;
    case (1)
        0: begin end
    endcase
endmodule

produces:

test.sv:2:11: warning: no case generate expression matches the value 1 [-Wcase-gen-none]
    case (1)
          ^


-Wconstraint-missing

An implicit class constraint block has no external definition and so is useless.

This diagnostic is enabled by default.

Example:

class C;
    constraint c;
endclass

produces:

test.sv:2:16: warning: no body for implicit constraint block 'c' [-Wconstraint-missing]
    constraint c;
               ^


-Wconversion

Controls -Wwidth-trunc, -Wwidth-expand, -Wimplicit-conv.

-Wdpi-spec

Old-style "DPI" specified subroutines are deprecated and not supported by slang. Use the new-style "DPI-C" which has a well-defined standardized calling convention.

This diagnostic is enabled by default.

Example:

import "DPI" function void foo();

produces:

test.sv:1:8: warning: 'DPI' specified subroutines are not supported and will be treated as 'DPI-C'. Note that this may require changes to the application's C code. [-Wdpi-spec]
import "DPI" function void foo();
       ^~~~~


-Wdup-attr

A design element has more than one attribute of the same name. Only the last one will apply.

Example:

module m;
    (* foo = 1, foo = 2 *)
    int i;
endmodule

produces:

test.sv:2:17: warning: duplicate attribute definition 'foo'; taking last value [-Wdup-attr]
    (* foo = 1, foo = 2 *)
                ^


-Wdup-import

A given scope contains more than one import statement for the same package and name.

Example:

package p;
    int i;
endpackage

module m;
    import p::i;
    import p::i;
endmodule

produces:

test.sv:7:15: warning: duplicate import declaration is redundant [-Wdup-import]
    import p::i;
              ^
test.sv:6:15: note: previous definition here
    import p::i;
              ^


-Wdynarray-index

A constant function tried to access a nonexistent element of a dynamic array.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    automatic int i[] = new [2];
    return i[4];
endfunction

produces:

test.sv:4:12: warning: invalid index 4 for 'dynamic array of int' of length 2 [-Wdynarray-index]
    return i[4];
           ^~~~
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^


-Wdynarray-range

A constant function tried to access a nonexistent range of a dynamic array.

This diagnostic is enabled by default.

Example:

typedef int ret_type[2];
localparam ret_type foo = func();
function ret_type func;
    automatic int i[] = new [2];
    return i[6:7];
endfunction

produces:

test.sv:5:12: warning: invalid range [6:7] for 'dynamic array of int' of length 2 [-Wdynarray-range]
    return i[6:7];
           ^~~~~~
test.sv:2:27: note: in call to 'func()'
localparam ret_type foo = func();
                          ^


-Welem-not-found

A constant function tried to access a nonexistent element of an associative array.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    int i[string];
    return i["Hello"];
endfunction

produces:

test.sv:4:14: warning: element "Hello" does not exist in associative array [-Welem-not-found]
    return i["Hello"];
           ~~^~~~~~~~
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^


-Wempty-member

An unnecessary semicolon is located in a non-procedural scope (such as a module body).

Example:

module m;
    ;
endmodule

produces:

test.sv:2:5: warning: extra ';' has no effect [-Wempty-member]
    ;
    ^


-Wempty-pattern

Issued for empty assignment pattern literals, which are not allowed by SystemVerilog but are supported by some tools.

Example:

int foo[] = '{};

produces:

test.sv:1:13: warning: empty assignment patterns are disallowed by SystemVerilog [-Wempty-pattern]
int foo[] = '{};
            ^


-Wempty-queue

A constant function tried to pop an element from an empty queue.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    automatic int i[$];
    return i.pop_back();
endfunction

produces:

test.sv:4:12: warning: pop from empty queue [-Wempty-queue]
    return i.pop_back();
           ^~~~~~~~~~
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^


-Wempty-stmt

An extra semicolon in a procedural context implies an empty statement that does nothing.

Example:

module m;
    initial begin
        ;
    end
endmodule

produces:

test.sv:3:9: warning: extra ';' has no effect [-Wempty-stmt]
        ;
        ^


-Wenum-range

An enum member is specified as a range with values that are not integer literals. The LRM does not allow other constant expressions to be used here.

This diagnostic is enabled by default.

Example:

localparam int i = 1;
typedef enum { A[i:3] } e_t;

produces:

test.sv:2:18: warning: enum element ranges must be integer literals [-Wenum-range]
typedef enum { A[i:3] } e_t;
                 ^


-Wevent-const

An event expression is a constant and so will never change.

This diagnostic is enabled by default.

Example:

module m;
    always @(1) begin
    end
endmodule

produces:

test.sv:2:14: warning: edge expression is constant [-Wevent-const]
    always @(1) begin
             ^


-Wexpected-diag-arg

Issued for a pragma diagnostic directive that is missing an argument.

This diagnostic is enabled by default.

Example:

`pragma diagnostic

produces:

test.sv:1:19: warning: expected diagnostic pragma argument [-Wexpected-diag-arg]
`pragma diagnostic
                  ^


-Wexplicit-static

static variables declared locally to a procedural block that contain an initializer require that the 'static' keyword be explicitly provided (and not just inferred from context) to clarify that the initialization happens only once. Most tools don't enforce this rule, so this is just a warning instead of an error.

This diagnostic is enabled by default.

Example:

module m;
    initial begin
        int i = 1;
    end
endmodule

produces:

test.sv:3:13: warning: initializing a static variable in a procedural context requires an explicit 'static' keyword [-Wexplicit-static]
        int i = 1;
            ^


-Wextra

Controls -Wempty-member, -Wempty-stmt, -Wdup-import, -Wpointless-void-cast, -Wcase-gen-none, -Wcase-gen-dup, -Wunused-result, -Wformat-real, -Wignored-slice, -Wtask-ignored, -Wwidth-trunc, -Wdup-attr.

-Wextra-pragma-args

Issued for a pragma directive that specifies more arguments than expected.

This diagnostic is enabled by default.

Example:

`pragma resetall extraarg

produces:

test.sv:1:18: warning: too many arguments provided for pragma 'resetall' [-Wextra-pragma-args]
`pragma resetall extraarg
                 ^


-Wfinish-num

The $finish control task accepts a "finish number" of 0, 1, or 2 as its first argument. The actual call to $finish in this case passed something other than one of those values.

This diagnostic is enabled by default.

Example:

module m;
    initial $finish("Hello");
endmodule

produces:

test.sv:2:21: warning: finish argument must have value of 0, 1, or 2 [-Wfinish-num]
    initial $finish("Hello");
                    ^~~~~~~


-Wformat-multibit-strength

Formatting multibit nets with the %v specifier is not allowed in SystemVerilog but most tools allow it anyway as an extension.

Example:

module m;
    wire [3:0] w;
    initial $display("%v", w);
endmodule

produces:

test.sv:3:28: warning: formatting strength values for multi-bit nets is non-standard [-Wformat-multibit-strength]
    initial $display("%v", w);
                      ~~   ^


-Wformat-real

A string formatting function was passed a real value for an integer format specifier, which will force the value to round to an integer.

Example:

module m;
    initial $display("%d", 3.14);
endmodule

produces:

test.sv:2:28: warning: real value provided for integer format specifier '%d' [-Wformat-real]
    initial $display("%d", 3.14);
                      ~~   ^~~~


-Wignored-macro-paste

Points out macro concatenation tokens that aren't actually concatenating anything due to whitespace on either side, or tokens that can't be concatenated in the first place.

Example:

`define FOO(a) a `` +
int foo;
int bar = `FOO(foo) foo;

produces:

test.sv:3:11: warning: paste token is pointless because it is adjacent to whitespace [-Wignored-macro-paste]
int bar = `FOO(foo) foo;
          ^
test.sv:1:18: note: expanded from macro 'FOO'
`define FOO(a) a `` +
                 ^


-Wignored-slice

A streaming operator with direction left-to-right provides a slice size, which has no effect because only right-to-left streaming can use a slice size.

Example:

int a;
int b = {>> 4 {a}};

produces:

test.sv:2:13: warning: slice size ignored for left-to-right streaming operator [-Wignored-slice]
int b = {>> 4 {a}};
            ^


-Wimplicit-conv

An implicit conversion in an expression converts between two unrelated types. SystemVerilog allows this for all packed integral types but it often indicates a mistake in the code.

This diagnostic is enabled by default.

Example:

module m;
    struct packed { logic a; int b; } foo;
    union packed { int a; int b; } bar;
    initial foo = bar;
endmodule

produces:

test.sv:4:17: warning: implicit conversion from '<unnamed packed union>' to '<unnamed packed struct>' [-Wimplicit-conv]
    initial foo = bar;
                ^ ~~~


-Wimplicit-net-port

A net port that elides its net type occurs in a context where ‘default_nettype is set to 'none’. This technically should be an error but it makes the use of 'none' as a default nettype very annoying and most tools just default to a wire in this case.

Example:

`default_nettype none

module m(input i);
endmodule

produces:

test.sv:3:16: warning: implicit net port disallowed because `default_nettype is set to 'none' [-Wimplicit-net-port]
module m(input i);
               ^


-Wineffective-sign

For a non-ANSI instance port or function body port declaration, the port I/O specifies a signing keyword but the actual data type of the port does not permit that signing to take effect.

Example:

module m(a);
    input unsigned a;
    int a;
endmodule

produces:

test.sv:2:11: warning: 'unsigned' on I/O declaration has no effect on type 'int' [-Wineffective-sign]
    input unsigned a;
          ^~~~~~~~
test.sv:3:9: note: declared here
    int a;
        ^


-Wint-overflow

Issued for integer literals that overflow a 32-bit integer (31-bits plus sign).

This diagnostic is enabled by default.

Example:

int i = 2147483648;

produces:

test.sv:1:9: warning: signed integer literal overflows 32 bits, will be truncated to -2147483648 [-Wint-overflow]
int i = 2147483648;
        ^


-Wlifetime-prototype

Lifetime specifiers are not allowed on method prototype declarations but some tools allow it as an extension.

This diagnostic is enabled by default.

Example:

class C;
    extern function automatic void foo;
endclass

function automatic void C::foo;
endfunction

produces:

test.sv:2:21: warning: lifetime specifier is not allowed on prototype declaration [-Wlifetime-prototype]
    extern function automatic void foo;
                    ^~~~~~~~~


-Wmissing-format

A string formatting function has a lone '%' at the end of the format string, implying that the rest of the specifier is missing. If a literal '%' is intended in the output, use the standard '%%' to achieve that.

This diagnostic is enabled by default.

Example:

module m;
    initial $display("Hello World %");
endmodule

produces:

test.sv:2:35: warning: missing format specifier [-Wmissing-format]
    initial $display("Hello World %");
                                  ^


-Wmissing-top

No valid top-level modules exist in the design. No top has been instantiated.

This diagnostic is enabled by default.

Example:

module m #(parameter int i);
endmodule

produces:

warning: no top-level modules found in design [-Wmissing-top]


-Wnet-inconsistent

A connection (or part of a connection) between an external net and an internal net port has inconsistent net types. The SystemVerilog LRM defines which combinations of net types are inconsistent and should produce a warning; see section [23.3.3.7] "Port connections with dissimilar net types (net and port collapsing)" for more detail.

This diagnostic is enabled by default.

Example:

module m (input .a({b, {c[1:0], d}}));
    wand b;
    wand [3:0] c;
    supply0 d;
endmodule

module top;
    wand a;
    wor b;
    trireg [1:0] c;
    m m1({a, b, c});
endmodule

produces:

test.sv:11:10: warning: net type 'wor' of connection bits [2:2] is inconsistent with net type 'wand' of corresponding port range [-Wnet-inconsistent]
    m m1({a, b, c});
         ^~~~~~~~~
test.sv:1:18: note: declared here
module m (input .a({b, {c[1:0], d}}));
                 ^


-Wnonblocking-final

A nonblocking assignment is used in a 'final' block, which will have no effect.

This diagnostic is enabled by default.

Example:

module m;
    int i;
    final begin
        i <= 1;
    end
endmodule

produces:

test.sv:4:9: warning: nonblocking assignments in final blocks have no effect [-Wnonblocking-final]
        i <= 1;
        ^~~~~~


-Wnonstandard-dist

'dist' constraint items are technically not allowed to be surrounded by parentheses according to the language grammar, but most tools allow it as an extension.

This diagnostic is enabled by default.

Example:

class C;
    rand bit a;
    rand bit [3:0] b;
    constraint cmd_c {
        a -> (b dist { 0 := 1, [1:15] := 1});
    }
endclass

produces:

test.sv:5:14: warning: use of parentheses around 'dist' expression is non-standard [-Wnonstandard-dist]
        a -> (b dist { 0 := 1, [1:15] := 1});
             ^                             ~


-Wnonstandard-escape-code

Detects use of '\%' in string literals. This is not a real escape code but other tools silently allow it anyway.

Example:

string s = "Hello World\%";

produces:

test.sv:1:24: warning: non-standard character escape sequence '\%' [-Wnonstandard-escape-code]
string s = "Hello World\%";
                       ^


-Wnonstandard-foreach

foreach loops are not allowed to have multidimensional brackets when declaring loop variables, but most tools allow it as an extension.

This diagnostic is enabled by default.

Example:

module top;
    int array[8][8];
    initial begin
        foreach (array[i]) begin
            foreach (array[i][j]) begin
                array[i][j] = i * j;
            end
        end
    end
endmodule

produces:

test.sv:5:22: warning: non-standard foreach loop variable list [-Wnonstandard-foreach]
            foreach (array[i][j]) begin
                     ^~~~~~~~


-Wnonstandard-generate

Indicates a standalone generate block (begin / end pair) without a corresponding generate loop or condition. This was allowed in older Verilog standards but is no longer allowed in SystemVerilog.

Example:

module m;
    begin : gen_block
        int i = 1;
    end
endmodule

produces:

test.sv:2:5: warning: standalone generate block without loop or condition is not allowed in SystemVerilog [-Wnonstandard-generate]
    begin : gen_block
    ^


-Wnonstandard-sys-func

Indicates a call to a nonstandard system function. Currently this only applies to the $psprintf function, which is a synonym for $sformatf.

This diagnostic is enabled by default.

Example:

module m;
    initial $psprintf("%d", 42);
endmodule

produces:

test.sv:2:13: warning: system function '$psprintf' is non-standard [-Wnonstandard-sys-func]
    initial $psprintf("%d", 42);
            ^~~~~~~~~~~~~~~~~~~


-Wpedantic

Controls -Wempty-pattern, -Wimplicit-net-port, -Wnonstandard-escape-code, -Wnonstandard-generate, -Wformat-multibit-strength, -Wnonstandard-sys-func, -Wnonstandard-foreach, -Wnonstandard-dist.

-Wpointless-void-cast

A function call is cast to 'void' but it already returns void so the cast is pointless.

Example:

module m;
    function void foo; endfunction
    initial begin
        void'(foo());
    end
endmodule

produces:

test.sv:4:15: warning: cast to void for void-returning function 'foo' has no effect [-Wpointless-void-cast]
        void'(foo());
              ^~~~~


-Wport-coercion

An input net port has been coerced to 'inout' direction because it is assigned to in the instance body. Alternatively, an output net port has been coerced to 'inout' direction because it is assigned to externally to the instance.

This diagnostic is enabled by default.

Example:

module m(input wire a, output b);
    assign a = 1;
endmodule

module n;
    wire b;
    m m1(1, b);
    assign b = 1;
endmodule

produces:

test.sv:2:12: warning: input net port 'a' coerced to 'inout' [-Wport-coercion]
    assign a = 1;
           ^
test.sv:1:21: note: declared here
module m(input wire a, output b);
                    ^
test.sv:7:13: warning: output net port 'b' coerced to 'inout' [-Wport-coercion]
    m m1(1, b);
            ^
test.sv:8:12: note: driven here
    assign b = 1;
           ^


-Wpragma-diag-level

Issued for a malformed diagnostic pragma. A severity code was expected where the given location is indicated.

This diagnostic is enabled by default.

Example:

`pragma diagnostic foo=3'd3

produces:

test.sv:1:20: warning: expected diagnostic severity (ignore,warn,error,fatal) [-Wpragma-diag-level]
`pragma diagnostic foo=3'd3
                   ^~~


-Wqueue-range

A constant function is accessing a queue with a reversed range, which is defined to always yield an empty queue.

This diagnostic is enabled by default.

Example:

typedef int ret_type[$];
localparam ret_type foo = func();
function ret_type func;
    automatic int i[$] = {1, 2, 3};
    return i[2:0];
endfunction

produces:

test.sv:5:12: warning: reversed selection range [2:0] for queue will always yield an empty result [-Wqueue-range]
    return i[2:0];
           ^~~~~~
test.sv:2:27: note: in call to 'func()'
localparam ret_type foo = func();
                          ^


-Wreal-overflow

Issued for real literals that are too large to be represented.

This diagnostic is enabled by default.

Example:

real r = 1.79769e+309;

produces:

test.sv:1:10: warning: value of real literal is too large; maximum is 1.79769e+308 [-Wreal-overflow]
real r = 1.79769e+309;
         ^


-Wreal-underflow

Issued for real literals that are too small to be represented.

This diagnostic is enabled by default.

Example:

real r = 4.94066e-325;

produces:

test.sv:1:10: warning: value of real literal is too small; minimum is 4.94066e-324 [-Wreal-underflow]
real r = 4.94066e-325;
         ^


-Wredef-macro

Issued for redefining a macro name with a different body.

This diagnostic is enabled by default.

Example:

`define FOO 1
`define FOO 2

produces:

test.sv:2:9: warning: macro 'FOO' redefined [-Wredef-macro]
`define FOO 2
        ^~~
test.sv:1:9: note: previous definition here
`define FOO 1
        ^


-Wstatic-skipped

A constant function contains a static variable with an initializer. That initializer will be skipped during constant evaluation, which could lead to unintuitive results.

This diagnostic is enabled by default.

Example:

localparam int foo = func();
function int func;
    static int i = 1;
    return i;
endfunction

produces:

test.sv:3:20: warning: static variable initialization is skipped in constant function calls [-Wstatic-skipped]
    static int i = 1;
                   ^
test.sv:1:22: note: in call to 'func()'
localparam int foo = func();
                     ^


-Wtask-ignored

A constant function contains a system task invocation which will be skipped during constant evaluation. This could yield unintuitive results.

Example:

localparam string foo = func();
function string func;
    automatic string s;
    $swrite(s, "asdf %d", 3);
    return s;
endfunction

produces:

test.sv:4:5: warning: system task '$swrite' is ignored in constant expression [-Wtask-ignored]
    $swrite(s, "asdf %d", 3);
    ^~~~~~~~~~~~~~~~~~~~~~~~
test.sv:1:25: note: in call to 'func()'
localparam string foo = func();
                        ^


-Wudp-port-empty

A connection to a user-defined primitive instance is an empty expression. While allowed, this is easily confused with a misplaced comma and is likely not what you want.

This diagnostic is enabled by default.

Example:

primitive p1 (output a, input b);
    table 00:0; endtable
endprimitive

module m;
    logic a;
    p1 (a,);
endmodule

produces:

test.sv:7:11: warning: primitive port connection is empty [-Wudp-port-empty]
    p1 (a,);
          ^


-Wunconnected-port

An instance port was left unconnected and it has no default value.

This diagnostic is enabled by default.

Example:

module m(input int i);
endmodule

module n;
    m m1();
endmodule

produces:

test.sv:5:7: warning: port 'i' has no connection [-Wunconnected-port]
    m m1();
      ^


-Wunconnected-unnamed-port

An unnamed instance port was left unconnected.

This diagnostic is enabled by default.

Example:

module m({a, b});
    input a, b;
endmodule

module n;
    m m1();
endmodule

produces:

test.sv:6:7: warning: instance does not provide a connection for an unnamed port [-Wunconnected-unnamed-port]
    m m1();
      ^
test.sv:1:10: note: declared here
module m({a, b});
         ^


-Wunknown-diag-arg

Issued for an unknown argument given to a pragma diagnostic directive.

This diagnostic is enabled by default.

Example:

`pragma diagnostic pushh

produces:

test.sv:1:20: warning: unknown diagnostic pragma argument 'pushh' [-Wunknown-diag-arg]
`pragma diagnostic pushh
                   ^~~~~


-Wunknown-escape-code

Detects use of unknown character escape codes in string literals.

This diagnostic is enabled by default.

Example:

string s = "Hello World\q";

produces:

test.sv:1:24: warning: unknown character escape sequence '\q' [-Wunknown-escape-code]
string s = "Hello World\q";
                       ^


-Wunknown-pragma

Issued for an unknown pragma directive.

This diagnostic is enabled by default.

Example:

`pragma foo

produces:

test.sv:1:9: warning: unknown pragma 'foo' [-Wunknown-pragma]
`pragma foo
        ^~~


-Wunsized-concat

An unsized type is used in a concatenation. This is not allowed in SystemVerilog but most tools allow it anyway as an extension.

This diagnostic is enabled by default.

Example:

longint i = {1, 2};

produces:

test.sv:1:14: warning: unsized integer in concat; using a width of 32 [-Wunsized-concat]
longint i = {1, 2};
             ^


-Wunused-def

A module, interface, or program definition is unused in the design.

Example:

module m #(parameter int i);
endmodule

module top;
endmodule

produces:

test.sv:1:8: warning: module definition is unused [-Wunused-def]
module m #(parameter int i);
       ^


-Wunused-result

A non-void function is invoked without inspecting its return value. Capture the result or cast the call to 'void' to suppress the warning.

Example:

module m;
    function int foo; return 1; endfunction
    initial begin
        foo();
    end
endmodule

produces:

test.sv:4:9: warning: ignoring return value of 'foo', cast to void to suppress [-Wunused-result]
        foo();
        ^~~~~


-Wvector-overflow

Issued for vector literals that are larger than their specified number of bits.

This diagnostic is enabled by default.

Example:

logic [7:0] i = 7'd256;

produces:

test.sv:1:20: warning: vector literal too large for the given number of bits [-Wvector-overflow]
logic [7:0] i = 7'd256;
                   ^


-Wwarning-task

A $warning elaboration task was encountered. Its message is printed by this diagnostic.

This diagnostic is enabled by default.

Example:

$warning("Hello World!");

produces:

test.sv:1:1: warning: $warning encountered: Hello World! [-Wwarning-task]
$warning("Hello World!");
^


-Wwidth-expand

An implicit conversion in an expression expands a type. This may be harmless, but the warning provides a mechanism for discovering unintended conversions. An explicit cast can be used to silence the warning.

Example:

logic [1:0] a;
int b = a;

produces:

test.sv:2:7: warning: implicit conversion expands from 2 to 32 bits [-Wwidth-expand]
int b = a;
      ^ ~


-Wwidth-trunc

An implicit conversion in an expression truncates a type. This conversion potentially loses data. An explicit cast can be used to silence the warning.

Example:

int a;
logic [1:0] b = a;

produces:

test.sv:2:15: warning: implicit conversion truncates from 32 to 2 bits [-Wwidth-trunc]
logic [1:0] b = a;
              ^ ~