template<typename TDerived, typename TState>
slang::analysis::AbstractFlowAnalysis class

An abstract class for flow analysis passes over SystemVerilog code.

This class provides a framework for implementing flow analysis passes by modeling control flow through the AST. Derived classes implement the actual state that gets tracked.

See background on lattice flow analysis: https://en.wikipedia.org/wiki/Data-flow_analysis https://clang.llvm.org/docs/DataFlowAnalysisIntro.html

Base classes

class FlowAnalysisBase
A base class for flow analysis passes that contains non-specialized helper functions.

Constructors, destructors, conversion operators

FlowAnalysisBase(const Symbol& symbol, AnalysisOptions options, Diagnostics* diagnostics = nullptr) protected
Constructs a new flow analysis pass.

Public functions

void run(const Statement& stmt)
Run the analysis.
void run(const Expression& expr)
Run the analysis.

Protected functions

auto getState() -> TState&
Gets the current flow state.
auto getState() const -> const TState&
Gets the current flow state.
void setState(TState newState)
Sets the current flow state to the given value.
void setConditionalState(TState whenTrue, TState whenFalse)
Puts the current state into a split conditional state, with the provided true and false state values.
void split()
Splits the current state into separate true / false states.
void unsplit()
Unsplits the current state if it was split by joining the true and false states.
void setUnreachable()
Sets the current state as unreachable.
auto getReturnStates() const -> std::span<const TState>
Gets the set of states at various return points in a subroutine.