slang::ast::IntegralType class

A base class for integral types, which include all scalar types, predefined integer types, packed arrays, packed structures, packed unions, and enum types.

Base classes

class Type
Base class for all data types in SystemVerilog.

Derived classes

class EnumType
Represents an enumerated type.
class PackedArrayType
Represents a packed array of some simple element type (vectors, packed structures, other packed arrays).
class PackedStructType
Represents a packed structure of members.
class PackedUnionType
Represents a packed union of members.
class PredefinedIntegerType
Represents the predefined integer types, which are essentially predefined vector types.
class ScalarType
Represents the single-bit scalar types.

Public functions

auto getBitVectorRange() const -> ConstantRange
If this is a simple bit vector type, returns the address range of the bits in the vector.
auto isDeclaredReg() const -> bool
Indicates whether the underlying type was declared using the 'reg' keyword.

Public variables

bitwidth_t bitWidth
The total width of the type in bits.
bool isSigned
Indicates whether or not the integer participates in signed arithmetic.
bool isFourState
Indicates whether the integer is composed of 4-state bits or 2-state bits.

Function documentation

ConstantRange slang::ast::IntegralType::getBitVectorRange() const

If this is a simple bit vector type, returns the address range of the bits in the vector.

Otherwise the behavior is undefined (will assert).