Statement creation and analysis.
- class slang::ast::Statement
- The base class for all statements in SystemVerilog.
- struct slang::ast::Statement::StatementContext
- Additional information passed along during statement creation.
- class slang::ast::InvalidStatement
- Represents an invalid statement, which is usually generated and inserted into a statement list due to violation of language semantics or type checking.
- class slang::ast::EmptyStatement
- Represents an empty statement, used as a placeholder or an anchor for attributes.
- class slang::ast::StatementList
- Represents a list of statements.
- class slang::ast::BlockStatement
- Represents a sequential or parallel block statement.
- struct slang::ast::ForeachLoopStatement::LoopDim
- Describes one dimension that will be iterated by the loop.